tx2bit._prj
来自「FPGA-CPLD_DesignTool(example5-6)」· _PRJ 代码 · 共 5 行
_PRJ
5 行
insert `timescale 1ns/1ns
include
include ../6-1/m2_1.v ../6-1/ddrfd.v ../6-1/load_gen.v ../6-1/piso.v ../6-1/tx2bit.v
include D:/Xilinx/verilog/src/iSE/unisim_comp.v
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