6_1pro.npl

来自「FPGA-CPLD_DesignTool(example5-6）」· NPL 代码 · 共 24 行

JDF E
// Created by ISE ver 1.0
PROJECT 6_1pro
DESIGN 6_1pro Normal
DEVKIT xcv1000e-6hq240
DEVFAM virtexe
FLOW XST Verilog
MODULE ..\6-1\load_gen.v
MODSTYLE load_gen Normal
MODULE ..\6-1\tx2bit.v
MODSTYLE tx2bit Normal
MODULE ..\6-1\piso.v
MODSTYLE piso Normal
MODULE ..\6-1\m2_1.v
MODSTYLE m2_1 Normal
MODULE ..\6-1\ddrfd.v
MODSTYLE ddrfd Normal
[STRATEGY-LIST]
Normal=True, 1039836240
[Normal]
xilxNgdbldUCF=xstvlg, VIRTEXE, Implementation.t_placeAndRouteDes, 1039939949, E:\work\6-1\tx2bit.ucf
xilxMapReportDetail=xstvlg, VIRTEXE, Implementation.t_placeAndRouteDes, 1039934399, True
xilxSynthKeepHierarchy=xstvlg, VIRTEXE, Schematic.t_synthesize, 1039937844, True