tx2bit.pcf

FPGA-CPLD_DesignTool(example5-6）

SCHEMATIC START ;
// created by map version E.35 on Tue Dec 17 10:05:37 2002 
COMP "ck" LOCATE = SITE "P113" LEVEL 1; 
COMP "clk" LOCATE = SITE "P213" LEVEL 1; 
COMP "ck_x" LOCATE = SITE "P114" LEVEL 1; 
COMP "clk4x" LOCATE = SITE "P89" LEVEL 1; 
COMP "da_x" LOCATE = SITE "P111" LEVEL 1; 
COMP "db_x" LOCATE = SITE "P118" LEVEL 1; 
COMP "da" LOCATE = SITE "P110" LEVEL 1; 
COMP "db" LOCATE = SITE "P117" LEVEL 1; 
NET "ddra/qrise" MAXDELAY = 600 pS  ;
NET "ddra/qrise" MAXSKEW = 50 pS  ;
NET "ddra/qfall" MAXDELAY = 600 pS  ;
NET "ddra/qfall" MAXSKEW = 50 pS  ;
NET "ddra/crr" MAXDELAY = 600 pS  ;
NET "ddra/crf" MAXDELAY = 600 pS  ;
NET "ddrb/qrise" MAXDELAY = 600 pS  ;
NET "ddrb/qrise" MAXSKEW = 50 pS  ;
NET "ddrb/qfall" MAXDELAY = 600 pS  ;
NET "ddrb/qfall" MAXSKEW = 50 pS  ;
NET "ddrb/crr" MAXDELAY = 600 pS  ;
NET "ddrb/crf" MAXDELAY = 600 pS  ;
NET "ddrc/qrise" MAXDELAY = 600 pS  ;
NET "ddrc/qrise" MAXSKEW = 50 pS  ;
NET "ddrc/crr" MAXDELAY = 600 pS  ;
NET "ddrc/crf" MAXDELAY = 600 pS  ;
TIMEGRP "clk4x" = BEL "ddra/ddr_fd1" BEL "ddra/ddr_fd2" BEL "ddra/ddr_fd3" BEL 
"ddra/ddr_fd4" BEL "ddra/ddr_ld1" BEL "ddra/ddr_ld2" BEL "ddrb/ddr_fd1" BEL 
"ddrb/ddr_fd2" BEL "ddrb/ddr_fd3" BEL "ddrb/ddr_fd4" BEL "ddrb/ddr_ld1" BEL 
"ddrb/ddr_ld2" BEL "ddrc/ddr_fd1" BEL "ddrc/ddr_fd3" BEL "ddrc/ddr_fd4" BEL 
"ddrc/ddr_ld1" BEL "ddrc/ddr_ld2" BEL "load_gen/load_FD_1" BEL 
"load_gen/load_FDR1" BEL "load_gen/load_FDR2" BEL "load_gen/load_FDR_1" BEL 
"load_gen/load_LDC_1" BEL "piso1/FDC1" BEL "piso1/FDC2" BEL "piso1/FDC3" BEL 
"piso1/FDC4" BEL "piso2/FDC3" BEL "piso2/FDC4" BEL "piso3/FDC1" BEL "piso3/FDC2"
 BEL "piso3/FDC3" BEL "piso3/FDC4" BEL "piso4/FDC1" BEL "piso4/FDC2" BEL 
"piso4/FDC3" BEL "piso4/FDC4" ;
TIMEGRP "ddr_fd3" = BEL "ddra/ddr_fd3" ; 
TIMEGRP "ddrd_ld" = BEL "ddra/ddr_ld1" BEL "ddra/ddr_ld2" BEL "ddrb/ddr_ld1" 
BEL "ddrb/ddr_ld2" BEL "ddrc/ddr_ld1" BEL "ddrc/ddr_ld2" ;
TIMEGRP "ddra_ld1" = BEL "ddra/ddr_ld1" ; 
TIMEGRP "clk" = BEL "load_gen/load_FDC1" BEL "load_gen/load_FDC2" ; 
TIMEGRP "FASTCLOCK" = TIMEGRP "clk4x" ; 
TIMEGRP "FASELATCH" = BEL "ddra/ddr_ld1" BEL "ddra/ddr_ld2" BEL "ddrb/ddr_ld1" 
BEL "ddrb/ddr_ld2" BEL "ddrc/ddr_ld1" BEL "ddrc/ddr_ld2" ;
TIMEGRP "SLOWCLOCK" = TIMEGRP "clk" ; 
TS_clk4x = PERIOD TIMEGRP "clk4x"  2 nS   HIGH 50.000000 % ;
TS_clk = PERIOD TIMEGRP "clk"  8 nS   HIGH 50.000000 % ;
TS_FST2FST = MAXDELAY FROM TIMEGRP "FASTCLOCK" TO TIMEGRP "FASTCLOCK" 3.800 nS ;
TS_FST2LAT = MAXDELAY FROM TIMEGRP "FASTCLOCK" TO TIMEGRP "FASELATCH" 3.800 nS ;
TS_LAT2LAT = MAXDELAY FROM TIMEGRP "FASELATCH" TO TIMEGRP "FASELATCH" 3.800 nS ;
TS_SLO2FST = MAXDELAY FROM TIMEGRP "SLOWCLOCK" TO TIMEGRP "FASTCLOCK" 8 nS  ; 
SCHEMATIC END ;