ddrfd.v

FPGA-CPLD_DesignTool(example5-6）

//+FHDR---------------------------------------------------------------------
// Copyright (c) 2002, zte.
// zte Confidential Proprietary
// --------------------------------------------------------------------------
// FILE NAME :ddrfd.v
// TYPE : module
// DEPARTMENT :
// AUTHOR : Xue Xiaogang 
// AUTHOR'S EMAIL : [e-mail]
// --------------------------------------------------------------------------
// Release history
// 
//   v00  2002-5-28 16:18  gen.
// --------------------------------------------------------------------------
// KEYWORDS : 
// --------------------------------------------------------------------------
// PURPOSE :   
//
// --------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME            RANGE : DESCRIPTION        : DEFAULT : VA UNITS
//  
// --------------------------------------------------------------------------
// REUSE ISSUES
// reset_b_b Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Function and task used :
// Other : 
//-FHDR--------------------------------------------------------------------

`timescale 1ns/1ps
module ddrfd(
    q,
    clk,
    d0,
    d1
    );
    
output q;
input clk;
input d0;
input d1;

FD   ddr_fd1 (.Q(qrise),  .C(clk),  .D(d0));
FD_1 ddr_fd2 (.Q(qfall),  .C(clk),  .D(d1));

LD   ddr_ld1 (.Q(lrr),    .G(clk),  .D(inv_lrf));
LD_1 ddr_ld2 (.Q(lrf),    .G(clk),  .D(lrr));

FD   ddr_fd3 (.Q(crr),    .C(clk),  .D(lrr));
FD_1 ddr_fd4 (.Q(crf),    .C(clk),  .D(lrf));

INV  ddr_inv (.O(inv_lrf), .I(lrf));

m2_1 ddr_m(.d0(qrise),  .d1(qfall),  .s0(qsel),   .o(q));
XOR2 ddr_xor(.O(qsel),   .I0(crf), .I1(crr));
FMAP  ddr_fmap(.I1(crr),  .I2(crf),  .I3(crf),  .I4(crr),  .O(qsel));

endmodule