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📄 tba_2470.mfd

📁 此文件是对xilinx95144器件编的程序
💻 MFD
📖 第 1 页 / 共 3 页
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123 
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<0>.PIN  | wr  | outputl_0_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 16
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   outputl<0>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<0>.PIN & 
	!(outputl_0_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<0>.PIN) & 
	outputl_0_obuf.FBK.LFBK;
   outputl<0>.CLK = !(wr);
   outputl<0>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 14 | outputl_1_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 14
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<1>.PIN  | wr  | outputl_1_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 14
INPUTP | 4 | 6 | 159 | 19 | 29
EQ | 8 | 
   outputl<1>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<1>.PIN & 
	!(outputl_1_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<1>.PIN) & 
	outputl_1_obuf.FBK.LFBK;
   outputl<1>.CLK = !(wr);
   outputl<1>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 13 | outputl_2_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 13
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<2>.PIN  | wr  | outputl_2_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 13
INPUTP | 4 | 6 | 159 | 21 | 29
EQ | 8 | 
   outputl<2>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<2>.PIN & 
	!(outputl_2_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<2>.PIN) & 
	outputl_2_obuf.FBK.LFBK;
   outputl<2>.CLK = !(wr);
   outputl<2>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 11 | outputl_3_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 11
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<3>.PIN  | wr  | outputl_3_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 11
INPUTP | 4 | 6 | 159 | 22 | 29
EQ | 8 | 
   outputl<3>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<3>.PIN & 
	!(outputl_3_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<3>.PIN) & 
	outputl_3_obuf.FBK.LFBK;
   outputl<3>.CLK = !(wr);
   outputl<3>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 10 | outputl_4_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 10
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<4>.PIN  | wr  | outputl_4_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 10
INPUTP | 4 | 6 | 159 | 23 | 29
EQ | 8 | 
   outputl<4>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<4>.PIN & 
	!(outputl_4_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<4>.PIN) & 
	outputl_4_obuf.FBK.LFBK;
   outputl<4>.CLK = !(wr);
   outputl<4>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 8 | outputl_5_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 8
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<5>.PIN  | wr  | outputl_5_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 8
INPUTP | 4 | 6 | 159 | 24 | 29
EQ | 8 | 
   outputl<5>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<5>.PIN & 
	!(outputl_5_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<5>.PIN) & 
	outputl_5_obuf.FBK.LFBK;
   outputl<5>.CLK = !(wr);
   outputl<5>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 7 | outputl_6_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 7
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<6>.PIN  | wr  | outputl_6_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 7
INPUTP | 4 | 6 | 159 | 26 | 29
EQ | 8 | 
   outputl<6>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<6>.PIN & 
	!(outputl_6_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<6>.PIN) & 
	outputl_6_obuf.FBK.LFBK;
   outputl<6>.CLK = !(wr);
   outputl<6>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 5 | outputl_7_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 5
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<7>  | wr  | outputl_7_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 5
INPUTP | 4 | 6 | 159 | 28 | 29
EQ | 6 | 
   outputl<7>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<7> & !(outputl_7_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<7>) & outputl_7_obuf.FBK.LFBK;
   outputl<7>.CLK = !(wr);
   outputl<7>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 4 | 4 | pa_c_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 4 | 4
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<0>.PIN  | wr  | pa_c_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 4 | 4
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 6 | 
   pa_c.T = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<0>.PIN & !(pa_c_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<0>.PIN) & pa_c_obuf.FBK.LFBK;
   pa_c.CLK = !(wr);
   pa_c.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 4 | play_s_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 6 | 4
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<0>.PIN  | wr  | play_s_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 4
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 6 | 
   play_s.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	inter_add<2> & !(inter_add<3>) & p0<0>.PIN & !(play_s_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	inter_add<2> & !(inter_add<3>) & !(p0<0>.PIN) & play_s_obuf.FBK.LFBK;
   play_s.CLK = !(wr);
   play_s.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 1 | stop_s_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 6 | 1
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<0>.PIN  | wr  | stop_s_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 1
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 6 | 
   stop_s.T = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & p0<0>.PIN & !(stop_s_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & !(p0<0>.PIN) & stop_s_obuf.FBK.LFBK;
   stop_s.CLK = !(wr);
   stop_s.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 16 | updown_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 6 | 16
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<0>.PIN  | wr  | updown_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 16
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 6 | 
   updown.T = !(cs) & !(reset) & inter_add<0> & inter_add<1> & 
	!(inter_add<2>) & !(inter_add<3>) & p0<0>.PIN & !(updown_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & inter_add<1> & 
	!(inter_add<2>) & !(inter_add<3>) & !(p0<0>.PIN) & updown_obuf.FBK.LFBK;
   updown.CLK = !(wr);
   updown.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 17 | inter_add<0>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 39 | 6 | 14 | 6 | 10 | 6 | 8 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 0 | 10 | 7 | 17 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3 | 5 | 3
INPUTS | 5 | cs  | p0<0>.PIN  | ale  | reset  | latch1/mtridata_dout<0>.FBK.LFBK
INPUTMC | 1 | 5 | 7
INPUTP | 4 | 6 | 18 | 2 | 159
EQ | 4 | 
   inter_add<0>.D = cs & latch1/mtridata_dout<0>.FBK.LFBK
	# !(cs) & p0<0>.PIN;
   inter_add<0>.CLK = !(ale);
   inter_add<0>.OE = !(reset);

MACROCELL | 5 | 15 | inter_add<1>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 38 | 6 | 14 | 6 | 10 | 6 | 8 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 0 | 10 | 7 | 17 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3
INPUTS | 5 | cs  | p0<1>.PIN  | ale  | reset  | latch1/mtridata_dout<1>.FBK.LFBK
INPUTMC | 1 | 5 | 6
INPUTP | 4 | 6 | 19 | 2 | 159
EQ | 4 | 
   inter_add<1>.D = cs & latch1/mtridata_dout<1>.FBK.LFBK
	# !(cs) & p0<1>.PIN;
   inter_add<1>.CLK = !(ale);
   inter_add<1>.OE = !(reset);

MACROCELL | 5 | 12 | inter_add<2>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 39 | 6 | 14 | 6 | 10 | 6 | 8 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 0 | 10 | 7 | 17 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3 | 5 | 3
INPUTS | 5 | cs  | p0<2>.PIN  | ale  | reset  | latch1/mtridata_dout<2>.FBK.LFBK
INPUTMC | 1 | 5 | 5
INPUTP | 4 | 6 | 21 | 2 | 159
EQ | 4 | 
   inter_add<2>.D = cs & latch1/mtridata_dout<2>.FBK.LFBK
	# !(cs) & p0<2>.PIN;
   inter_add<2>.CLK = !(ale);
   inter_add<2>.OE = !(reset);

MACROCELL | 5 | 9 | inter_add<3>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 39 | 6 | 14 | 6 | 10 | 6 | 8 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 0 | 1 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 0 | 10 | 7 | 17 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3
INPUTS | 5 | cs  | p0<3>.PIN  | ale  | reset  | latch1/mtridata_dout<3>.FBK.LFBK
INPUTMC | 1 | 5 | 4
INPUTP | 4 | 6 | 22 | 2 | 159
EQ | 4 | 
   inter_add<3>.D = cs & latch1/mtridata_dout<3>.FBK.LFBK
	# !(cs) & p0<3>.PIN;
   inter_add<3>.CLK = !(ale);
   inter_add<3>.OE = !(reset);

MACROCELL | 0 | 1 | p0_0_iobufe$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 6 | p0_0_iobufe  | cs  | reset  | inter_add<3>  | rd  | $OpTx$$OpTx$FX_DC$17_INV$27
INPUTMC | 2 | 5 | 9 | 5 | 3
INPUTP | 3 | 6 | 159 | 30
EQ | 3 | 
   p0<0> = p0_0_iobufe;
   p0<0>.OE = !(cs) & !(reset) & !(inter_add<3>) & !(rd) & 
	!($OpTx$$OpTx$FX_DC$17_INV$27);
123

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