📄 reg2_4.rpt
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(unused) 0 0 0 5 FB7_10 (b)
(unused) 0 0 0 5 FB7_11 58 I/O
(unused) 0 0 0 5 FB7_12 60 I/O
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 61 I/O
(unused) 0 0 0 5 FB7_15 62 I/O
(unused) 0 0 0 5 FB7_16 (b)
(unused) 0 0 0 5 FB7_17 63 I/O
(unused) 0 0 0 5 FB7_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB8_1 (b)
(unused) 0 0 0 5 FB8_2 65 I/O
(unused) 0 0 0 5 FB8_3 (b)
(unused) 0 0 0 5 FB8_4 (b)
(unused) 0 0 0 5 FB8_5 66 I/O I
(unused) 0 0 0 5 FB8_6 67 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 68 I/O
(unused) 0 0 0 5 FB8_9 69 I/O
(unused) 0 0 0 5 FB8_10 (b)
(unused) 0 0 0 5 FB8_11 70 I/O
(unused) 0 0 0 5 FB8_12 72 I/O
(unused) 0 0 0 5 FB8_13 (b)
(unused) 0 0 0 5 FB8_14 73 I/O
(unused) 0 0 0 5 FB8_15 74 I/O
(unused) 0 0 0 5 FB8_16 (b)
(unused) 0 0 0 5 FB8_17 75 I/O
(unused) 0 0 0 5 FB8_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
!dout<0>.D = cs & !(dout_0.FBK.LFBK)
# !(din<2>) & !(din<1>) & !(din<0>) & !(cs);
!dout<0>.CLK = wr; // GCK
dout<0>.AP = reset; // GSR
!dout<1>.D = cs & !(dout_1.FBK.LFBK)
# !(din<2>) & !(din<1>) & din<0> & !(cs);
!dout<1>.CLK = wr; // GCK
dout<1>.AP = reset; // GSR
!dout<2>.D = cs & !(dout_2.FBK.LFBK)
# !(din<2>) & din<1> & !(din<0>) & !(cs);
!dout<2>.CLK = wr; // GCK
dout<2>.AP = reset; // GSR
!dout<3>.D = cs & !(dout_3.FBK.LFBK)
# !(din<2>) & din<1> & din<0> & !(cs);
!dout<3>.CLK = wr; // GCK
dout<3>.AP = reset; // GSR
**************************** Device Pin Out ****************************
Device : XC95144-7-PQ100
d
o
u
t
V T T T T T T T T V < T T G T T T T T
C c I I I I I I I I C 2 I I N D I I I I
C s E E E E E E E E C > E E D O E E E E
----------------------------------------
/100 98 96 94 92 90 88 86 84 82 \
| 99 97 95 93 91 89 87 85 83 81 |
reset | 1 80 | TIE
GND | 2 79 | TIE
TIE | 3 78 | TIE
TIE | 4 77 | GND
TIE | 5 76 | din<0>
TIE | 6 75 | TIE
VCC | 7 74 | TIE
TIE | 8 73 | TIE
TIE | 9 72 | TIE
TIE | 10 71 | GND
TIE | 11 70 | TIE
TIE | 12 69 | TIE
dout<3> | 13 XC95144-7-PQ100 68 | TIE
TIE | 14 67 | TIE
TIE | 15 66 | din<2>
TIE | 16 65 | TIE
TIE | 17 64 | GND
TIE | 18 63 | TIE
TIE | 19 62 | TIE
TIE | 20 61 | TIE
TIE | 21 60 | TIE
TIE | 22 59 | VCC
GND | 23 58 | TIE
wr | 24 57 | TIE
TIE | 25 56 | TIE
dout<1> | 26 55 | TIE
TIE | 27 54 | TIE
VCC | 28 53 | VCC
TIE | 29 52 | TIE
TIE | 30 51 | TIE
| 32 34 36 38 40 42 44 46 48 50 |
\31 33 35 37 39 41 43 45 47 49 /
----------------------------------------
T T G d T T d T T V T T T T T G T T T T
I I N i I I o I I C I I I I I N D I M C
E E D n E E u E E C E E E E E D I E S K
< t
1 <
> 0
>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC95144-7-PQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Slew Rate : FAST
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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