📄 reg2_4.rpt
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cpldfit: version F.31 Xilinx Inc.
Fitter Report
Design Name: reg2_4 Date: 8-11-2004, 8:19PM
Device Used: XC95144-7-PQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
4 /144 ( 3%) 8 /720 ( 1%) 4 /144 ( 3%) 10 /81 ( 12%) 20 /288 ( 7%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 4 4 | I/O : 8 65
Output : 4 4 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 1 1 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 10 10
MACROCELL RESOURCES:
Total Macrocells Available 144
Registered Macrocells 4
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
The complement of 'wr' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'reset' mapped onto global set/reset net GSR.
POWER DATA:
There are 4 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 4 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
dout<0> 2 5 FB5_2 STD FAST 37 I/O O RESET
dout<1> 2 5 FB3_5 STD FAST 26 I/O O RESET
dout<2> 2 5 FB4_2 STD FAST 89 I/O O RESET
dout<3> 2 5 FB1_2 STD FAST 13 I/O O RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
cs FB4_17 99 I/O I
din<0> FB6_2 76 I/O I
din<1> FB3_14 34 I/O I
din<2> FB8_5 66 I/O I
reset FB2_2 1 GSR/I/O GSR
wr FB1_17 24 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 1 5 5 2 1/0 11
FB2 0 0 0 0 0/0 10
FB3 1 5 5 2 1/0 10
FB4 1 5 5 2 1/0 10
FB5 1 5 5 2 1/0 10
FB6 0 0 0 0 0/0 10
FB7 0 0 0 0 0/0 10
FB8 0 0 0 0 0/0 10
---- ----- ----- -----
4 8 4/0 81
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/31
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
dout<3> 2 0 0 3 FB1_2 STD 13 I/O O
(unused) 0 0 0 5 FB1_3 14 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 15 I/O
(unused) 0 0 0 5 FB1_6 16 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 17 I/O
(unused) 0 0 0 5 FB1_9 18 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 19 I/O
(unused) 0 0 0 5 FB1_12 20 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 21 I/O
(unused) 0 0 0 5 FB1_15 22 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 24 GCK/I/O GCK
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: dout_3.FBK.LFBK
2: din<0> 4: din<2>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
dout<3> XXXXX................................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 1 GSR/I/O GSR
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 3 GTS/I/O
(unused) 0 0 0 5 FB2_6 4 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 8 I/O
(unused) 0 0 0 5 FB2_12 9 I/O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 10 I/O
(unused) 0 0 0 5 FB2_15 11 I/O
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 12 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 5/31
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 25 GCK/I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
dout<1> 2 0 0 3 FB3_5 STD 26 I/O O
(unused) 0 0 0 5 FB3_6 27 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 29 GCK/I/O
(unused) 0 0 0 5 FB3_9 30 I/O
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