d4_16.tim

此文件是对xilinx95144器件编的程序

                           Performance Summary Report
                           --------------------------

Design:     d4_16
Device:     XC95144-7-PQ100
Speed File: Version 3.0
Program:    Timing Report Generator:  version F.31
Date:       Wed Aug 11 10:34:18 2004

Performance Summary:

Pad to Pad (tPD)                          :          7.5ns (1 macrocell levels)
Pad 'cs' to Pad 'cs_out<0>'                                       

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From         c     d     d     d     d     r
 \             s     i     i     i     i     e
  \                  n     n     n     n     s
   \                 <     <     <     <     e
    \                0     1     2     3     t
     \               >     >     >     >      
      \                                       
       \                                      
        \                                     
         \                                    
  To      \------------------------------------

cs_out<0>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<10>   7.5   7.5   7.5   7.5   7.5   7.5
cs_out<11>   7.5   7.5   7.5   7.5   7.5   7.5
cs_out<12>   7.5   7.5   7.5   7.5   7.5   7.5
cs_out<13>   7.5   7.5   7.5   7.5   7.5   7.5
cs_out<14>   7.5   7.5   7.5   7.5   7.5   7.5
cs_out<15>   7.5   7.5   7.5   7.5   7.5   7.5
cs_out<1>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<2>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<3>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<4>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<5>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<6>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<7>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<8>    7.5   7.5   7.5   7.5   7.5   7.5
cs_out<9>    7.5   7.5   7.5   7.5   7.5   7.5

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU or tSUF) -     Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and ends at register 
                                          (Fast Input Register for tSUF) D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. Pin-to-pin setup 
                                          requirement is not reported or 
                                          guaranteed for product-term clocks 
                                          derived from macrocell feedback 
                                          signals. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.