📄 tba_2472.tim
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Performance Summary Report
--------------------------
Design: tba_2472
Device: XC95144-7-PQ100
Speed File: Version 3.0
Program: Timing Report Generator: version F.31
Date: Wed Aug 11 11:48:17 2004
Performance Summary:
Pad to Pad (tPD) : 18.0ns (2 macrocell levels)
Pad 'playing' to Pad 'p0<0>'
Clock net 'ale' path delays:
Clock Pad to Output Pad (tCO) : 31.5ns (3 macrocell levels)
Clock Pad 'ale' to Output Pad 'p0<0>' (Pterm Clock)
Setup to Clock at the Pad (tSU) : 0.5ns (0 macrocell levels)
Data signal 'p0<0>' to DFF D input Pin at 'inter_add<0>.D'
Clock pad 'ale' (Pterm Clock)
Minimum Clock Period: 10.0ns
Maximum Internal Clock Speed: 100.0Mhz
(Limited by Clock Pulse Width)
Clock net 'wr' path delays:
Clock Pad to Output Pad (tCO) : 8.5ns (1 macrocell levels)
Clock Pad 'wr' to Output Pad 'en485' (Pterm Clock)
Clock to Setup (tCYC) : 8.0ns (1 macrocell levels)
Clock to Q, net 'en485.Q' to TFF Setup(D) at 'en485.D' (Pterm Clock)
Target FF drives output net 'en485_obuf$Q'
Setup to Clock at the Pad (tSU) : 0.5ns (0 macrocell levels)
Data signal 'cs' to TFF D input Pin at 'en485.D'
Clock pad 'wr' (Pterm Clock)
Minimum Clock Period: 10.0ns
Maximum Internal Clock Speed: 100.0Mhz
(Limited by Clock Pulse Width)
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From c m n p r r r s s s s s
\ s _ o l a d e p p p p p
\ s f a d s e e e e e
\ _ i y i e e e e e e
\ i l i o t d d d d d
\ n e n < < < < <
\ g 0 1 2 3 4
\ > > > > >
To \------------------------------------------------------------------------
p0<0> 9.5 18.0 18.0 18.0 18.0 9.5 9.5 18.0
p0<1> 9.5 9.5 9.5 7.5
p0<2> 9.5 9.5 9.5 7.5
p0<3> 9.5 9.5 9.5 7.5
p0<4> 9.5 9.5 9.5 7.5
p0<5> 9.5 9.5 9.5
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From s
\ p
\ e
\ e
\ d
\ <
\ 5
\ >
To \------
p0<0>
p0<1>
p0<2>
p0<3>
p0<4>
p0<5> 7.5
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From a w
\ l r
\ e
\
\
\
\
\
\
\
To \------------
check<0> 8.5
check<1> 8.5
check<2> 8.5
en485 8.5
lcd_c 8.5
led1 8.5
led<2> 8.5
led<3> 8.5
led<4> 8.5
led<5> 8.5
load 8.5
m_s_out 8.5
outputh<8> 8.5
outputh<9> 8.5
outputl<0> 8.5
outputl<1> 8.5
outputl<2> 8.5
outputl<3> 8.5
outputl<4> 8.5
outputl<5> 8.5
outputl<6> 8.5
outputl<7> 8.5
p0<0> 31.5
p0<1> 21.0
p0<2> 21.0
p0<3> 21.0
p0<4> 21.0
p0<5> 21.0
pa_c 8.5
play_s 8.5
stop_s 8.5
updown 8.5
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU or tSUF) (nsec)
\ From a w
\ l r
\ e
\
\
\
\
To \------------
cs 0.5
p0<0> 0.5 0.5
p0<1> 0.5 0.5
p0<2> 0.5 0.5
p0<3> 0.5 0.5
p0<4> 0.5
p0<5> 0.5
p0<6> 0.5
p0<7> 0.5
reset 0.5
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: wr)
\ From e l l l l l l l m o o
\ n c e e e e e o _ u u
\ 4 d d d d d d a s t t
\ 8 _ 1 < < < < d _ p p
\ 5 c . 2 3 4 5 . o u u
\ . . Q > > > > Q u t t
\ Q Q . . . . t h h
\ Q Q Q Q . < <
\ Q 8 9
\ > >
\ . .
\ Q Q
To \------------------------------------------------------------------
en485.D 8.0
lcd_c.D 8.0
led1.D 8.0
led<2>.D 8.0
led<3>.D 8.0
led<4>.D 8.0
led<5>.D 8.0
load.D 8.0
m_s_out.D 8.0
outputh<8>.D 8.0
outputh<9>.D 8.0
outputl<0>.D
outputl<1>.D
outputl<2>.D
outputl<3>.D
outputl<4>.D
outputl<5>.D
outputl<6>.D
outputl<7>.D
pa_c.D
play_s.D
stop_s.D
updown.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: wr)
\ From o o o o o o o o p p s
\ u u u u u u u u a l t
\ t t t t t t t t _ a o
\ p p p p p p p p c y p
\ u u u u u u u u . _ _
\ t t t t t t t t Q s s
\ l l l l l l l l . .
\ < < < < < < < < Q Q
\ 0 1 2 3 4 5 6 7
\ > > > > > > > >
\ . . . . . . . .
\ Q Q Q Q Q Q Q Q
To \------------------------------------------------------------------
en485.D
lcd_c.D
led1.D
led<2>.D
led<3>.D
led<4>.D
led<5>.D
load.D
m_s_out.D
outputh<8>.D
outputh<9>.D
outputl<0>.D 8.0
outputl<1>.D 8.0
outputl<2>.D 8.0
outputl<3>.D 8.0
outputl<4>.D 8.0
outputl<5>.D 8.0
outputl<6>.D 8.0
outputl<7>.D 8.0
pa_c.D 8.0
play_s.D 8.0
stop_s.D 8.0
updown.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: wr)
\ From u
\ p
\ d
\ o
\ w
\ n
\ .
\ Q
\
\
\
\
To \------
en485.D
lcd_c.D
led1.D
led<2>.D
led<3>.D
led<4>.D
led<5>.D
load.D
m_s_out.D
outputh<8>.D
outputh<9>.D
outputl<0>.D
outputl<1>.D
outputl<2>.D
outputl<3>.D
outputl<4>.D
outputl<5>.D
outputl<6>.D
outputl<7>.D
pa_c.D
play_s.D
stop_s.D
updown.D 8.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and ends at register
(Fast Input Register for tSUF) D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers. Pin-to-pin setup
requirement is not reported or
guaranteed for product-term clocks
derived from macrocell feedback
signals.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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