📄 tba_2470.tim
字号:
\ u u u u
\ t t t t
\ < < < <
\ 0 1 2 3
\ > > > >
\ . . . .
\ Q Q Q Q
To \------------------------
inter_add<0>.D 8.0
inter_add<1>.D 8.0
inter_add<2>.D 8.0
inter_add<3>.D 8.0
latch1/mtridata_dout<0>.D 8.0
latch1/mtridata_dout<1>.D 8.0
latch1/mtridata_dout<2>.D 8.0
latch1/mtridata_dout<3>.D 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: wr)
\ From c c c e l l l l l l l
\ h h h n c e e e e e o
\ e e e 4 d d d d d d a
\ c c c 8 _ 1 < < < < d
\ k k k 5 c . 2 3 4 5 .
\ < < < . . Q > > > > Q
\ 0 1 2 Q Q . . . .
\ > > > Q Q Q Q
\ . . .
\ Q Q Q
\
\
To \------------------------------------------------------------------
check<0>.D 8.0
check<1>.D 8.0
check<2>.D 8.0
en485.D 8.0
lcd_c.D 8.0
led1.D 8.0
led<2>.D 8.0
led<3>.D 8.0
led<4>.D 8.0
led<5>.D 8.0
load.D 8.0
m_s_out.D
outputh<8>.D
outputh<9>.D
outputl<0>.D
outputl<1>.D
outputl<2>.D
outputl<3>.D
outputl<4>.D
outputl<5>.D
outputl<6>.D
outputl<7>.D
pa_c.D
play_s.D
stop_s.D
updown.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: wr)
\ From m o o o o o o o o o o
\ _ u u u u u u u u u u
\ s t t t t t t t t t t
\ _ p p p p p p p p p p
\ o u u u u u u u u u u
\ u t t t t t t t t t t
\ t h h l l l l l l l l
\ . < < < < < < < < < <
\ Q 8 9 0 1 2 3 4 5 6 7
\ > > > > > > > > > >
\ . . . . . . . . . .
\ Q Q Q Q Q Q Q Q Q Q
To \------------------------------------------------------------------
check<0>.D
check<1>.D
check<2>.D
en485.D
lcd_c.D
led1.D
led<2>.D
led<3>.D
led<4>.D
led<5>.D
load.D
m_s_out.D 8.0
outputh<8>.D 8.0
outputh<9>.D 8.0
outputl<0>.D 8.0
outputl<1>.D 8.0
outputl<2>.D 8.0
outputl<3>.D 8.0
outputl<4>.D 8.0
outputl<5>.D 8.0
outputl<6>.D 8.0
outputl<7>.D 8.0
pa_c.D
play_s.D
stop_s.D
updown.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: wr)
\ From p p s u
\ a l t p
\ _ a o d
\ c y p o
\ . _ _ w
\ Q s s n
\ . . .
\ Q Q Q
\
\
\
\
To \------------------------
check<0>.D
check<1>.D
check<2>.D
en485.D
lcd_c.D
led1.D
led<2>.D
led<3>.D
led<4>.D
led<5>.D
load.D
m_s_out.D
outputh<8>.D
outputh<9>.D
outputl<0>.D
outputl<1>.D
outputl<2>.D
outputl<3>.D
outputl<4>.D
outputl<5>.D
outputl<6>.D
outputl<7>.D
pa_c.D 8.0
play_s.D 8.0
stop_s.D 8.0
updown.D 8.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and ends at register
(Fast Input Register for tSUF) D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers. Pin-to-pin setup
requirement is not reported or
guaranteed for product-term clocks
derived from macrocell feedback
signals.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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