tba_2470.gfl

此文件是对xilinx95144器件编的程序

reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Assign Package Pins
tba_2472.cmd_log
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# Implmentation : Translate (CPLD flow)
__projnav/regd_edfTOngd_tcl.rsp
regd.ngd
regd.bld
regd_ngdbuild.nav
_ngo/netlist.lst
.untf
regd_html
regd.cmd_log
# Implmentation : Generate Timing
__projnav/regd_vm6TOtim_tcl.rsp
regd.tim
regd.mod
regd.data
regd.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/regd_ngdTOvm6_tcl.rsp
regd.vm6
regd.cxt
regd.blx
regd.mfd
regd.rpt
regd.log
regd.pnx
regd.gyd
regd.xml
regd_build.xml
tba_2470.ptf
regd.bl
errors.xml
tmperr.err
regd.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# Implmentation : Translate (CPLD flow)
__projnav/regd_edfTOngd_tcl.rsp
regd.ngd
regd.bld
regd_ngdbuild.nav
_ngo/netlist.lst
.untf
regd_html
regd.cmd_log
# Implmentation : Generate Timing
__projnav/regd_vm6TOtim_tcl.rsp
regd.tim
regd.mod
regd.data
regd.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/regd_ngdTOvm6_tcl.rsp
regd.vm6
regd.cxt
regd.blx
regd.mfd
regd.rpt
regd.log
regd.pnx
regd.gyd
regd.xml
regd_build.xml