tba_2470.gfl

来自「此文件是对xilinx95144器件编的程序」· GFL 代码 · 共 3,960 行 · 第 1/5 页

latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# View Fitted Design (ChipViewer)
tba_2472.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# Generate Programming File (CPLD flow)
__projnav/tba_2472_vm6TOjed_tcl.rsp
tba_2472.jed
tba_2472.isc
tba_2472.cmd_log
# Configure Device (iMPACT)
tba_2472.prm
tba_2472.isc
tba_2472.svf
xilinx.sys
tba_2472.mcs
tba_2472.exo
tba_2472.hex
tba_2472.tek
tba_2472.dst
tba_2472.dst_compressed
tba_2472.mpm
EndScriptMarker
0
# View Fitted Design (ChipViewer)
tba_2472.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# Generate Programming File (CPLD flow)
__projnav/tba_2472_vm6TOjed_tcl.rsp
tba_2472.jed
tba_2472.isc
tba_2472.cmd_log
# Configure Device (iMPACT)
tba_2472.prm
tba_2472.isc
tba_2472.svf
xilinx.sys
tba_2472.mcs
tba_2472.exo
tba_2472.hex
tba_2472.tek
tba_2472.dst
tba_2472.dst_compressed
tba_2472.mpm
EndScriptMarker
0
# Configure Device (iMPACT)
tba_2472.prm
tba_2472.isc
tba_2472.svf
xilinx.sys
tba_2472.mcs
tba_2472.exo
tba_2472.hex
tba_2472.tek
tba_2472.dst
tba_2472.dst_compressed
tba_2472.mpm
EndScriptMarker
0
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# Generate Programming File (CPLD flow)
__projnav/tba_2472_vm6TOjed_tcl.rsp
tba_2472.jed
tba_2472.isc
tba_2472.cmd_log
# Configure Device (iMPACT)
tba_2472.prm
tba_2472.isc
tba_2472.svf
xilinx.sys
tba_2472.mcs
tba_2472.exo
tba_2472.hex
tba_2472.tek
tba_2472.dst
tba_2472.dst_compressed
tba_2472.mpm
EndScriptMarker
0
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr