tba_2470.gfl

此文件是对xilinx95144器件编的程序

# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/reg_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_4_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_3_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg2_3_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba_2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba_2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2470.syr
tba_2470.ngr
tba_2470.prj
tba_2470.sprj
tba_2470.ana
tba_2470.stx
tba_2470.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba_2472_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba_2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba_2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba_2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2470.syr
tba_2470.ngr
tba_2470.prj
tba_2470.sprj
tba_2470.ana
tba_2470.stx
tba_2470.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/reg_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# xst flow : RunXST
reg.syr
reg.ngr
reg.prj
reg.sprj
reg.ana
reg.stx
reg.cmd_log
reg.ngc
# xst flow : RunXST
reg2_3.syr
reg2_3.ngr
reg2_3.prj
reg2_3.sprj
reg2_3.ana
reg2_3.stx
reg2_3.cmd_log
reg2_3.ngc
# xst flow : RunXST
reg2_4.syr
reg2_4.ngr
reg2_4.prj
reg2_4.sprj
reg2_4.ana
reg2_4.stx
reg2_4.cmd_log
reg2_4.ngc
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# Implmentation : Translate (CPLD flow)
__projnav/d4_16_edfTOngd_tcl.rsp
d4_16.ngd
d4_16.bld
d4_16_ngdbuild.nav
_ngo/netlist.lst
.untf
d4_16_html
d4_16.cmd_log
# Implmentation : Generate Timing
__projnav/d4_16_vm6TOtim_tcl.rsp
d4_16.tim
d4_16.mod
d4_16.data
d4_16.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/d4_16_ngdTOvm6_tcl.rsp
d4_16.vm6
d4_16.cxt
d4_16.blx
d4_16.mfd
d4_16.rpt
d4_16.log
d4_16.pnx
d4_16.gyd
d4_16.xml
d4_16_build.xml
tba_2470.ptf
d4_16.bl
errors.xml
tmperr.err
d4_16.cmd_log
# Implmentation : FitRpt
d4_16_html
d4_16._hrpt
d4_16.cmd_log
# View Fitted Design (ChipViewer)
d4_16.cmd_log
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Assign Package Pins
tba_2472.cmd_log
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# View Fitted Design (ChipViewer)
tba_2472.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
regd.syr
regd.ngr
regd.prj
regd.sprj
regd.ana
regd.stx
regd.cmd_log
regd.ngc
# Implmentation : Translate (CPLD flow)
__projnav/regd_edfTOngd_tcl.rsp
regd.ngd
regd.bld
regd_ngdbuild.nav
_ngo/netlist.lst
.untf
regd_html
regd.cmd_log
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# Implmentation : Translate (CPLD flow)
__projnav/tba_2472_edfTOngd_tcl.rsp
tba_2472.ngd
tba_2472.bld
tba_2472_ngdbuild.nav
_ngo/netlist.lst
tba_2472.ucf.untf
tba_2472_html
tba_2472.cmd_log
# Implmentation : Generate Timing
__projnav/tba_2472_vm6TOtim_tcl.rsp
tba_2472.tim
tba_2472.mod
tba_2472.data
tba_2472.cmd_log
__projnav\taengine.err
# Implmentation : Fit
__projnav/tba_2472_ngdTOvm6_tcl.rsp
tba_2472.vm6
tba_2472.cxt
tba_2472.blx
tba_2472.mfd
tba_2472.rpt
tba_2472.log
tba_2472.pnx
tba_2472.gyd
tba_2472.xml
tba_2472_build.xml
tba_2470.ptf
tba_2472.bl
errors.xml
tmperr.err
tba_2472.cmd_log
# Implmentation : FitRpt
tba_2472_html
tba_2472._hrpt
tba_2472.cmd_log
# View Fitted Design (ChipViewer)
tba_2472.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/latch_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/latch_jhdparse_tcl.rsp
# xst flow : RunXST
latch.syr
latch.ngr
latch.prj
latch.sprj
latch.ana
latch.stx
latch.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/latch_jhdparse_tcl.rsp
# xst flow : RunXST
latch.syr
latch.ngr
latch.prj
latch.sprj
latch.ana
latch.stx
latch.cmd_log
latch.ngc
# VHDL : PDCL (jhdparse)
__projnav/latch_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# xst flow : RunXST
d4_16.syr
d4_16.ngr
d4_16.prj
d4_16.sprj
d4_16.ana
d4_16.stx
d4_16.cmd_log
d4_16.ngc
# Implmentation : Translate (CPLD flow)
__projnav/d4_16_edfTOngd_tcl.rsp
d4_16.ngd
d4_16.bld
d4_16_ngdbuild.nav
_ngo/netlist.lst
.untf
d4_16_html
d4_16.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/d4_16_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc
latch.ngc
reg.ngc
reg2_3.ngc
reg2_4.ngc
regd.ngc
tba_2472.ngc
# VHDL : PDCL (jhdparse)
__projnav/tba-2472_jhdparse_tcl.rsp
# xst flow : RunXST
tba_2472.syr
tba_2472.ngr
tba_2472.prj
tba_2472.sprj
tba_2472.ana
tba_2472.stx
tba_2472.cmd_log
d4_16.ngc