latch.vhd

来自「此文件是对xilinx95144器件编的程序」· VHDL 代码 · 共 26 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity latch is
    generic (size:integer:=1);
    Port (cs,ale,reset: in std_logic;
	        din: in std_logic_vector(size-1 downto 0);
	 			dout : out std_logic_vector(size-1 downto 0)
	 		 );
end latch;

architecture Behavioral of latch is
begin
MAIN: process(cs,ale,reset,din)
begin
	if reset = '1' then
		dout <=(others=> 'Z');
	elsif ale'event and ale = '0' then
		if cs = '0' then
			dout <= din;
		end if;
	end if;
end process;

end Behavioral;