reg.vhd

来自「此文件是对xilinx95144器件编的程序」· VHDL 代码 · 共 27 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg is
    generic (size:integer:=1);
    Port (cs,wr,reset: in std_logic;
	        din: in std_logic_vector(size-1 downto 0);
	 			dout : out std_logic_vector(size-1 downto 0)
	 		 );
end reg;

architecture Behavioral of reg is
	begin
		process(wr,cs,reset)
			begin
				if reset = '1' then
					dout <=(others=> '1');
				elsif cs = '0' then
					if wr'event and wr = '0' then
						dout <= din;
					end if;
				end if;
		end process;
end Behavioral;