📄 tba_2470.rpt
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Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 32/4
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB8_1 (b)
outputh<9> 3 0 0 2 FB8_2 STD 65 I/O O
(unused) 0 0 0 5 FB8_3 (b)
p0_0_iobufe$WA5 2 0 0 3 FB8_4 STD (b) (b)
outputh<8> 3 0 0 2 FB8_5 STD 66 I/O O
outputl<7> 3 0 0 2 FB8_6 STD 67 I/O O
p0_0_iobufe$WA4 2 0 0 3 FB8_7 STD (b) (b)
outputl<6> 3 0 0 2 FB8_8 STD 68 I/O O
outputl<5> 3 0 0 2 FB8_9 STD 69 I/O O
p0_0_iobufe$WA3 2 0 0 3 FB8_10 STD (b) (b)
outputl<4> 3 0 0 2 FB8_11 STD 70 I/O O
outputl<3> 3 0 0 2 FB8_12 STD 72 I/O O
p0_0_iobufe$WA2 2 0 0 3 FB8_13 STD (b) (b)
outputl<2> 3 0 0 2 FB8_14 STD 73 I/O O
outputl<1> 3 0 0 2 FB8_15 STD 74 I/O O
p0_0_iobufe$WA1 2 0 0 3 FB8_16 STD (b) (b)
outputl<0> 3 0 0 2 FB8_17 STD 75 I/O O
p0_0_iobufe$WA0 2 0 0 3 FB8_18 STD (b) (b)
Signals Used by Logic in Function Block
1: cs 12: p0<4>.PIN 23: outputl_5_obuf.FBK.LFBK
2: inter_add<0> 13: p0<5>.PIN 24: outputl_6_obuf.FBK.LFBK
3: inter_add<1> 14: p0<6>.PIN 25: outputl_7_obuf.FBK.LFBK
4: inter_add<2> 15: nofile 26: p0<7>
5: inter_add<3> 16: outputh_8_obuf.FBK.LFBK
27: playing
6: lcd_in 17: outputh_9_obuf.FBK.LFBK
28: radio
7: m_s_in 18: outputl_0_obuf.FBK.LFBK
29: rd
8: p0<0>.PIN 19: outputl_1_obuf.FBK.LFBK
30: reset
9: p0<1>.PIN 20: outputl_2_obuf.FBK.LFBK
31: speed<0>
10: p0<2>.PIN 21: outputl_3_obuf.FBK.LFBK
32: wr
11: p0<3>.PIN 22: outputl_4_obuf.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
outputh<9> XXXXX...X.......X............X.X........ 9 9
p0_0_iobufe$WA5 XXXXXX......................XX.......... 8 8
outputh<8> XXXXX..X.......X.............X.X........ 9 9
outputl<7> XXXXX...................XX...X.X........ 9 9
p0_0_iobufe$WA4 XXXXX.....................X.XX.......... 8 8
outputl<6> XXXXX........X.........X.....X.X........ 9 9
outputl<5> XXXXX.......X.........X......X.X........ 9 9
p0_0_iobufe$WA3 XXXXX.........X.............XX.......... 8 8
outputl<4> XXXXX......X.........X.......X.X........ 9 9
outputl<3> XXXXX.....X.........X........X.X........ 9 9
p0_0_iobufe$WA2 XXXXX......................XXX.......... 8 8
outputl<2> XXXXX....X.........X.........X.X........ 9 9
outputl<1> XXXXX...X.........X..........X.X........ 9 9
p0_0_iobufe$WA1 XXXXX.X.....................XX.......... 8 8
outputl<0> XXXXX..X.........X...........X.X........ 9 9
p0_0_iobufe$WA0 XXXXX.......................XXX......... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
$OpTx$$OpTx$FX_DC$17_INV$27 = inter_add<0> & inter_add<2>;
check<0>.T = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & p0<1>.PIN & !(check_0_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & p0<0>.PIN & !(check_0_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & !(p0<1>.PIN) & !(p0<0>.PIN) &
check_0_obuf.FBK.LFBK;
check<0>.CLK = !(wr);
check<0>.AP = reset; // GSR
check<1>.T = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & p0<1>.PIN & !(check_1_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & !(p0<0>.PIN) & !(check_1_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & !(p0<1>.PIN) & p0<0>.PIN &
check_1_obuf.FBK.LFBK;
check<1>.CLK = !(wr);
check<1>.AP = reset; // GSR
check<2>.T = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & !(p0<1>.PIN) & !(check_2_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & p0<0>.PIN & !(check_2_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & inter_add<3> & p0<1>.PIN & !(p0<0>.PIN) &
check_2_obuf.FBK.LFBK;
check<2>.CLK = !(wr);
check<2>.AP = reset; // GSR
dled1 = Vcc;
dled2 = Vcc;
dled3 = Vcc;
en485.T = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
!(inter_add<2>) & !(inter_add<3>) & p0<0>.PIN & !(en485_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
!(inter_add<2>) & !(inter_add<3>) & !(p0<0>.PIN) & en485_obuf.FBK.LFBK;
en485.CLK = !(wr);
en485.AP = reset; // GSR
inter_add<0>.D = cs & latch1/mtridata_dout<0>.FBK.LFBK
# !(cs) & p0<0>.PIN;
inter_add<0>.CLK = !(ale);
inter_add<0>.OE = !(reset);
inter_add<1>.D = cs & latch1/mtridata_dout<1>.FBK.LFBK
# !(cs) & p0<1>.PIN;
inter_add<1>.CLK = !(ale);
inter_add<1>.OE = !(reset);
inter_add<2>.D = cs & latch1/mtridata_dout<2>.FBK.LFBK
# !(cs) & p0<2>.PIN;
inter_add<2>.CLK = !(ale);
inter_add<2>.OE = !(reset);
inter_add<3>.D = cs & latch1/mtridata_dout<3>.FBK.LFBK
# !(cs) & p0<3>.PIN;
inter_add<3>.CLK = !(ale);
inter_add<3>.OE = !(reset);
latch1/mtridata_dout<0>.D = cs & latch1/mtridata_dout<0>.FBK.LFBK
# !(cs) & p0<0>.PIN;
latch1/mtridata_dout<0>.CLK = !(ale);
latch1/mtridata_dout<1>.D = cs & latch1/mtridata_dout<1>.FBK.LFBK
# !(cs) & p0<1>.PIN;
latch1/mtridata_dout<1>.CLK = !(ale);
latch1/mtridata_dout<2>.D = cs & latch1/mtridata_dout<2>.FBK.LFBK
# !(cs) & p0<2>.PIN;
latch1/mtridata_dout<2>.CLK = !(ale);
latch1/mtridata_dout<3>.D = cs & latch1/mtridata_dout<3>.FBK.LFBK
# !(cs) & p0<3>.PIN;
latch1/mtridata_dout<3>.CLK = !(ale);
lcd_c.T = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & !(inter_add<3>) & p0<0>.PIN & !(lcd_c_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
inter_add<2> & !(inter_add<3>) & !(p0<0>.PIN) & lcd_c_obuf.FBK.LFBK;
lcd_c.CLK = !(wr);
lcd_c.AP = reset; // GSR
led1.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & !(inter_add<3>) & p0<0>.PIN & !(led1_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & !(inter_add<3>) & !(p0<0>.PIN) & led1_obuf.FBK.LFBK;
led1.CLK = !(wr);
led1.AP = reset; // GSR
led<2>.T = !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<1>.PIN & !(led_2_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<2>.PIN & !(led_2_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<0>.PIN & !(led_2_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & !(p0<1>.PIN) & !(p0<2>.PIN) &
!(p0<0>.PIN) & led_2_obuf.FBK.LFBK;
led<2>.CLK = !(wr);
led<2>.AP = reset; // GSR
led<3>.T = !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<1>.PIN & !(led_3_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<2>.PIN & !(led_3_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & !(p0<0>.PIN) & !(led_3_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & !(p0<1>.PIN) & !(p0<2>.PIN) &
p0<0>.PIN & led_3_obuf.FBK.LFBK;
led<3>.CLK = !(wr);
led<3>.AP = reset; // GSR
led<4>.T = !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & !(p0<1>.PIN) & !(led_4_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<2>.PIN & !(led_4_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<0>.PIN & !(led_4_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<1>.PIN & !(p0<2>.PIN) &
!(p0<0>.PIN) & led_4_obuf.FBK.LFBK;
led<4>.CLK = !(wr);
led<4>.AP = reset; // GSR
led<5>.T = !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & !(p0<1>.PIN) & !(led_5_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<2>.PIN & !(led_5_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & !(p0<0>.PIN) & !(led_5_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<1>.PIN & !(p0<2>.PIN) &
p0<0>.PIN & led_5_obuf.FBK.LFBK;
led<5>.CLK = !(wr);
led<5>.AP = reset; // GSR
load.T = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
!(inter_add<2>) & !(inter_add<3>) & p0<0>.PIN & !(load_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
!(inter_add<2>) & !(inter_add<3>) & !(p0<0>.PIN) & load_obuf.FBK.LFBK;
load.CLK = !(wr);
load.AP = reset; // GSR
m_s_out.T = !(cs) & !(reset) & inter_add<0> & inter_add<1> &
inter_add<2> & !(inter_add<3>) & p0<0>.PIN & !(m_s_out_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & inter_add<1> &
inter_add<2> & !(inter_add<3>) & !(p0<0>.PIN) & m_s_out_obuf.FBK.LFBK;
m_s_out.CLK = !(wr);
m_s_out.AP = reset; // GSR
outputh<8>.T = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<0>.PIN &
!(outputh_8_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
!(inter_add<2>) & inter_add<3> & !(p0<0>.PIN) &
outputh_8_obuf.FBK.LFBK;
outputh<8>.CLK = !(wr);
outputh<8>.AP = reset; // GSR
outputh<9>.T = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
!(inter_add<2>) & inter_add<3> & p0<1>.PIN &
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