📄 tba_2470.rpt
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(unused) 0 0 0 5 FB3_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 9/27
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
dled1 0 0 0 5 FB4_2 STD 89 I/O O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
dled2 0 0 0 5 FB4_5 STD 91 I/O O
dled3 0 0 0 5 FB4_6 STD 92 I/O O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 93 I/O
en485 3 0 0 2 FB4_9 STD 94 I/O O
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 95 I/O
(unused) 0 0 0 5 FB4_12 96 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 97 I/O
(unused) 0 0 0 5 FB4_15 98 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 99 I/O
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: cs 4: inter_add<1> 7: p0<0>.PIN
2: en485_obuf.FBK.LFBK
5: inter_add<2> 8: reset
3: inter_add<0> 6: inter_add<3> 9: wr
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
dled1 ........................................ 0 0
dled2 ........................................ 0 0
dled3 ........................................ 0 0
en485 XXXXXXXXX............................... 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 37 I/O I
(unused) 0 0 0 5 FB5_3 (b)
(unused) 0 0 0 5 FB5_4 (b)
pa_c 3 0 0 2 FB5_5 STD 38 I/O O
m_s_out 3 0 0 2 FB5_6 STD 39 I/O O
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 41 I/O I
(unused) 0 0 0 5 FB5_9 42 I/O I
(unused) 0 0 0 5 FB5_10 (b)
(unused) 0 0 0 5 FB5_11 43 I/O I
(unused) 0 0 0 5 FB5_12 44 I/O I
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 45 I/O I
(unused) 0 0 0 5 FB5_15 48 I/O I
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 51 I/O I
(unused) 0 0 0 5 FB5_18 (b)
Signals Used by Logic in Function Block
1: cs 5: inter_add<3> 8: pa_c_obuf.FBK.LFBK
2: inter_add<0> 6: m_s_out_obuf.FBK.LFBK
9: reset
3: inter_add<1> 7: p0<0>.PIN 10: wr
4: inter_add<2>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
pa_c XXXXX.XXXX.............................. 9 9
m_s_out XXXXXXX.XX.............................. 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 22/14
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 76 I/O I
(unused) 0 0 0 5 FB6_3 (b)
$OpTx$$OpTx$FX_DC$17_INV$27
1 0 0 4 FB6_4 STD (b) (b)
latch1/mtridata_dout<3>
3 0 0 2 FB6_5 STD 78 I/O (b)
latch1/mtridata_dout<2>
3 0 0 2 FB6_6 STD 79 I/O (b)
latch1/mtridata_dout<1>
3 0 0 2 FB6_7 STD (b) (b)
latch1/mtridata_dout<0>
3 0 0 2 FB6_8 STD 80 I/O (b)
load 3 0 0 2 FB6_9 STD 81 I/O O
inter_add<3> 4 0 0 1 FB6_10 STD (b) (b)
led<5> 5 0 0 0 FB6_11 STD 82 I/O O
led<4> 5 0 0 0 FB6_12 STD 83 I/O O
inter_add<2> 4 0 0 1 FB6_13 STD (b) (b)
led<3> 5 0 0 0 FB6_14 STD 84 I/O O
led<2> 5 0 0 0 FB6_15 STD 87 I/O O
inter_add<1> 4 0 0 1 FB6_16 STD (b) (b)
led1 3 0 0 2 FB6_17 STD 88 I/O O
inter_add<0> 4 0 0 1 FB6_18 STD (b) (b)
Signals Used by Logic in Function Block
1: ale 9: latch1/mtridata_dout<2>.FBK.LFBK
16: load_obuf.FBK.LFBK
2: cs 10: latch1/mtridata_dout<3>.FBK.LFBK
17: p0<0>.PIN
3: inter_add<0> 11: led1_obuf.FBK.LFBK
18: p0<1>.PIN
4: inter_add<1> 12: led_2_obuf.FBK.LFBK
19: p0<2>.PIN
5: inter_add<2> 13: led_3_obuf.FBK.LFBK
20: p0<3>.PIN
6: inter_add<3> 14: led_4_obuf.FBK.LFBK
21: reset
7: latch1/mtridata_dout<0>.FBK.LFBK
15: led_5_obuf.FBK.LFBK
22: wr
8: latch1/mtridata_dout<1>.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
$OpTx$$OpTx$FX_DC$17_INV$27
..X.X................................... 2 2
latch1/mtridata_dout<3>
XX.......X.........X.................... 4 4
latch1/mtridata_dout<2>
XX......X.........X..................... 4 4
latch1/mtridata_dout<1>
XX.....X.........X...................... 4 4
latch1/mtridata_dout<0>
XX....X.........X....................... 4 4
load .XXXXX.........XX...XX.................. 9 9
inter_add<3> XX.......X.........XX................... 5 5
led<5> .XXXXX........X.XXX.XX.................. 11 11
led<4> .XXXXX.......X..XXX.XX.................. 11 11
inter_add<2> XX......X.........X.X................... 5 5
led<3> .XXXXX......X...XXX.XX.................. 11 11
led<2> .XXXXX.....X....XXX.XX.................. 11 11
inter_add<1> XX.....X.........X..X................... 5 5
led1 .XXXXX....X.....X...XX.................. 9 9
inter_add<0> XX....X.........X...X................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 16/20
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB7_1 (b)
stop_s 3 0 0 2 FB7_2 STD 52 I/O O
(unused) 0 0 0 5 FB7_3 (b)
(unused) 0 0 0 5 FB7_4 (b)
play_s 3 0 0 2 FB7_5 STD 54 I/O O
(unused) 0 0 0 5 FB7_6 55 I/O I
(unused) 0 0 0 5 FB7_7 (b)
lcd_c 3 0 0 2 FB7_8 STD 56 I/O O
check<2> 4 0 0 1 FB7_9 STD 57 I/O O
(unused) 0 0 0 5 FB7_10 (b)
check<1> 4 0 0 1 FB7_11 STD 58 I/O O
(unused) 0 0 0 5 FB7_12 60 I/O I
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 61 I/O I
check<0> 4 0 0 1 FB7_15 STD 62 I/O O
(unused) 0 0 0 5 FB7_16 (b)
updown 3 0 0 2 FB7_17 STD 63 I/O O
(unused) 0 0 0 5 FB7_18 (b)
Signals Used by Logic in Function Block
1: check_0_obuf.FBK.LFBK
7: inter_add<2> 12: play_s_obuf.FBK.LFBK
2: check_1_obuf.FBK.LFBK
8: inter_add<3> 13: reset
3: check_2_obuf.FBK.LFBK
9: lcd_c_obuf.FBK.LFBK
14: stop_s_obuf.FBK.LFBK
4: cs 10: p0<0>.PIN 15: updown_obuf.FBK.LFBK
5: inter_add<0> 11: p0<1>.PIN 16: wr
6: inter_add<1>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
stop_s ...XXXXX.X..XX.X........................ 9 9
play_s ...XXXXX.X.XX..X........................ 9 9
lcd_c ...XXXXXXX..X..X........................ 9 9
check<2> ..XXXXXX.XX.X..X........................ 10 10
check<1> .X.XXXXX.XX.X..X........................ 10 10
check<0> X..XXXXX.XX.X..X........................ 10 10
updown ...XXXXX.X..X.XX........................ 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
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