tba_2472.vhd

此文件是对xilinx95144器件编的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tba_2470 is
    Port ( p0 : inout std_logic_vector(7 downto 0);
           clk,wr,rd,cs,ale,reset: in std_logic;
			  playing,nofile,radio,m_s_in: in std_logic;
           en485,led1,load, updown,lcd_c,play_s,stop_s,m_s_out,pa_c,dled1,dled2,dled3: out std_logic;
				led	 :out std_logic_vector(5 downto 2);
           outputl : out std_logic_vector(7 downto 0);
			  outputh: out std_logic_vector(9 downto 8);
			  check :  out std_logic_vector(2 downto 0);
           SPEED : in std_logic_vector(5 downto 0));
end tba_2470;
architecture Behavioral of tba_2470 is
    --signal  inter_add: std_logic_vector(3 downto 0);
    signal  cs_reg:    std_logic_vector(15 downto 0);
component reg
    generic (size:integer:=1);
    Port (cs,wr,reset: in std_logic;
	        din: in std_logic_vector(size-1 downto 0);
	 			dout : out std_logic_vector(size-1 downto 0)
	 		 );
end component;
--component latch
 --   generic (size:integer:=1);
 --   Port (cs,wr,reset: in std_logic;
	--        din: in std_logic_vector(size-1 downto 0);
	 --			dout : out std_logic_vector(size-1 downto 0)
	 --		 );
--end component;
component regd
  generic (size:integer:=1);
   Port (cs,rd: in std_logic;
	        din: in std_logic_vector(size-1 downto 0);
	 			dout : out std_logic_vector(size-1 downto 0)
	 		 );
end component;
component d4_16
    Port ( ale,cs,reset : in std_logic;
			  din: IN std_logic_vector(3 DOWNTO 0);
           cs_out : OUT std_logic_vector(15 downto 0)
	 		 );
end component;
component reg2_4
    Port (cs,wr,reset : in std_logic;       
			 din: IN std_logic_vector(2 DOWNTO 0);
           dout : out std_logic_vector(3 downto 0) );
end component;
component reg2_3
    Port ( cs,wr,reset : in std_logic;       
			  din:  in  std_logic_vector(1 downto 0);
           dout :  out std_logic_vector(2 downto 0));
end component;
begin
decode4: d4_16	 port map (ale,cs,reset,din(3 downto 0)=>p0(3 downto 0),cs_out=>cs_reg);
reg1_0: reg     generic map(1)
                port map(cs=>cs_reg(0),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>en485);
reg1_1: reg   	 generic map(1)
 				    port map(cs=>cs_reg(1),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>led1);
reg1_2: reg     generic map(1)
                port map(cs=>cs_reg(2),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>load);
reg1_3: reg     generic map(1)
	             port map(cs=>cs_reg(3),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>updown);
reg1_4: reg     generic map(1)
				    port map(cs=>cs_reg(4),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>lcd_c);
reg1_5: reg     generic map(1)
				    Port map(cs=>cs_reg(5),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>play_s);
reg1_6: reg   	 generic map(1)
 				    port map(cs=>cs_reg(6),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>stop_s);
reg1_7: reg     generic map(1)
                port map(cs=>cs_reg(7),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>m_s_out);
reg1_8: reg     generic map(1)
                port map(cs=>cs_reg(8),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>pa_c);
reg8_1: reg     generic map(8)
                port map(cs_reg(9),wr,reset,p0,outputl);
--latch1: reg      generic map(4)
  --              port map( wr,ale,reset ,p0(3 downto 0),inter_add);  
reg2_1: reg     generic map(2)
                port map(cs=>cs_reg(10),wr=>wr,reset=>reset,din(1 downto 0)=>p0(1 downto 0),
					         dout(1 downto 0)=>outputh(9 downto 8));
reg4_1: reg2_4   port map(cs=>cs_reg(11),wr=>wr,reset=>reset,din(2 downto 0)=>p0(2 downto 0),
					         dout=>led);
reg3_1: reg2_3   port map(cs=>cs_reg(12),wr=>wr,reset=>reset,din(1 downto 0)=>p0(1 downto 0),dout=>check);
reg1_13: reg     generic map(1)
                 port map(cs=>cs_reg(13),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>dled1);
reg1_14: reg     generic map(1)
                 port map(cs=>cs_reg(14),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>dled2);
reg1_15: reg     generic map(1)
                 port map(cs=>cs_reg(15),wr=>wr,reset=>reset,din(0)=>p0(0),dout(0)=>dled3);
regd_6: regd     generic map(6)
                 port map(cs=>cs_reg(6),rd=>rd,din=>speed,dout(5 downto 0)=>p0(5 downto 0));
regd1_1:  regd    generic map(1)
                  port map(cs=>cs_reg(0),rd=>rd,din(0)=>playing,dout(0)=>p0(0)); 
regd1_2:  regd    generic map(1)
                  port map(cs=>cs_reg(1),rd=>rd,din(0)=>nofile,dout(0)=>p0(0)); 
regd1_3:  regd    generic map(1)
                  port map(cs=>cs_reg(2),rd=>rd,din(0)=>radio,dout(0)=>p0(0)); 
regd1_4:  regd    generic map(1)
                  port map(cs=>cs_reg(3),rd=>rd,din(0)=>m_s_in,dout(0)=>p0(0)); 

end Behavioral;