regd1.mod

此文件是对xilinx95144器件编的程序

MODEL
MODEL_VERSION "v1998.8";
DESIGN "regd1";

/* port names and type */
INPUT S:PIN24 = rd;
INPUT S:PIN99 = cs;
INPUT S:PIN66 = din;
OUTPUT S:PIN13 = dout;

/* timing arc definitions */
rd_dout_delay: DELAY rd dout;

/* timing check arc definitions */
cs_rd_setup: SETUP(POSEDGE) cs rd;
din_rd_setup: SETUP(POSEDGE) din rd;
cs_rd_hold: HOLD(POSEDGE) cs rd;
din_rd_hold: HOLD(POSEDGE) din rd;

ENDMODEL