reg2_3.vhd

来自「此文件是对xilinx95144器件编的程序」· VHDL 代码 · 共 30 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg2_3 is
    Port ( cs,wr,reset : in std_logic;       
			  din:  in  std_logic_vector(1 downto 0);
           dout :  out std_logic_vector(2 downto 0));
end reg2_3;
architecture Behavioral of reg2_3 is
signal indate: std_logic_vector(1 downto 0);
begin
 indate<=din;
process(cs,wr,reset,din)
begin
if  reset='1' then
        dout<="111";
   elsif ( wr'event AND wr='0') then
	        if (cs='0' ) then
                    case indate is
                       when "00" => dout <= "110";	  --0
                       when "01" => dout <= "101";	  --1
                       when "10" => dout <= "011";    --2
	    	              when others => dout<="111";
                   end case;
			 else  dout<="111";	
       end if;
	end if;
end process; 
end Behavioral;