tba_2472.syr

此文件是对xilinx95144器件编的程序

Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: tba_2472.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : tba_2472.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : tba_2472
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Entity Name                        : tba_2472
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower

---- Other Options
cross_clock_analysis               : NO
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/tba2472BCPLD源程序/d4_16.vhd in Library work.
Architecture behavioral of Entity d4_16 is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/reg.vhd in Library work.
Architecture behavioral of Entity reg is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/latch.vhd in Library work.
Architecture behavioral of Entity latch is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/reg2_4.vhd in Library work.
Architecture behavioral of Entity reg2_4 is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/reg2_3.vhd in Library work.
Architecture behavioral of Entity reg2_3 is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/regd.vhd in Library work.
Architecture behavioral of Entity regd is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/regd1.vhd in Library work.
Architecture behavioral of Entity regd1 is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/tba-2472.vhd in Library work.
ERROR:HDLParsers:500 - G:/tba2472BCPLD源程序/tba-2472.vhd Line 91. Identifier p0 is used as positional after a named instantiation.
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Total memory usage is 45784 kilobytes