regd1.vhd

此文件是对xilinx95144器件编的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity regd1 is
    Port (cs,rd: in std_logic;
	        din: in std_logic;
	 			dout : out std_logic
		--	ledd:out std_logic_vector(3 downto 0)
	 		 );
end regd1;

architecture Behavioral of regd1 is

begin

MAIN: process(rd,cs,din)
begin
    		--ledd(0) <= '0';
		if rd'event and rd = '0' then
		    if cs = '0' then
		    	dout <= din;
		--	ledd(1) <= '0';
	--	else
	--		 ledd(1) <= '1';
		end if;

--	else ledd(0) <= '1';
	     --ledd(1) <= '1';
    end if;
end process;
--process(cs,rd)
--begin
--	 if cs = '0' then
--	     if rd = '1' then
--		    ledd(1) <= '1';
--		end if;
--	end if;
    
--end process;
end Behavioral ;