d4_16.syr

此文件是对xilinx95144器件编的程序

Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: d4_16.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : d4_16.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : d4_16
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Entity Name                        : d4_16
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower

---- Other Options
cross_clock_analysis               : NO
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/d4_16.vhd in Library work.
Entity <d4_16> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <d4_16> (Architecture <behavioral>).
INFO:Xst:1561 - D:/郑玉静/信箱/tba_2470/d4_16.vhd line 41: Mux is complete : default of case is discarded
Entity <d4_16> analyzed. Unit <d4_16> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <d4_16>.
    Related source file is D:/郑玉静/信箱/tba_2470/d4_16.vhd.
Unit <d4_16> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <d4_16> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : d4_16.ngr
Top Level Output File Name         : d4_16
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : YES
Macro Generator                    : macro+
Target Technology                  : xc9500
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 22

Cell Usage :
# BELS                             : 54
#      INV                         : 20
#      OR2                         : 25
#      OR3                         : 8
#      OR4                         : 1
# IO Buffers                       : 22
#      IBUF                        : 6
#      OBUF                        : 16
=========================================================================
CPU : 0.41 / 0.63 s | Elapsed : 1.00 / 1.00 s
 
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Total memory usage is 57164 kilobytes