regd.rpt
来自「此文件是对xilinx95144器件编的程序」· RPT 代码 · 共 498 行 · 第 1/2 页
RPT
498 行
(unused) 0 0 0 5 FB5_3 (b)
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 38 I/O
(unused) 0 0 0 5 FB5_6 39 I/O
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 41 I/O
(unused) 0 0 0 5 FB5_9 42 I/O
(unused) 0 0 0 5 FB5_10 (b)
(unused) 0 0 0 5 FB5_11 43 I/O
(unused) 0 0 0 5 FB5_12 44 I/O
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 45 I/O
(unused) 0 0 0 5 FB5_15 48 I/O
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 51 I/O
(unused) 0 0 0 5 FB5_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 76 I/O
(unused) 0 0 0 5 FB6_3 (b)
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 78 I/O
(unused) 0 0 0 5 FB6_6 79 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 80 I/O
(unused) 0 0 0 5 FB6_9 81 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 82 I/O
(unused) 0 0 0 5 FB6_12 83 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 84 I/O
(unused) 0 0 0 5 FB6_15 87 I/O
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 88 I/O
(unused) 0 0 0 5 FB6_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 52 I/O
(unused) 0 0 0 5 FB7_3 (b)
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 54 I/O
(unused) 0 0 0 5 FB7_6 55 I/O
(unused) 0 0 0 5 FB7_7 (b)
(unused) 0 0 0 5 FB7_8 56 I/O
(unused) 0 0 0 5 FB7_9 57 I/O
(unused) 0 0 0 5 FB7_10 (b)
(unused) 0 0 0 5 FB7_11 58 I/O
(unused) 0 0 0 5 FB7_12 60 I/O
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 61 I/O
(unused) 0 0 0 5 FB7_15 62 I/O
(unused) 0 0 0 5 FB7_16 (b)
(unused) 0 0 0 5 FB7_17 63 I/O
(unused) 0 0 0 5 FB7_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB8_1 (b)
led4 0 0 0 5 FB8_2 STD 65 I/O O
(unused) 0 0 0 5 FB8_3 (b)
(unused) 0 0 0 5 FB8_4 (b)
(unused) 0 0 0 5 FB8_5 66 I/O I
(unused) 0 0 0 5 FB8_6 67 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 68 I/O
(unused) 0 0 0 5 FB8_9 69 I/O
(unused) 0 0 0 5 FB8_10 (b)
(unused) 0 0 0 5 FB8_11 70 I/O
(unused) 0 0 0 5 FB8_12 72 I/O
(unused) 0 0 0 5 FB8_13 (b)
(unused) 0 0 0 5 FB8_14 73 I/O
(unused) 0 0 0 5 FB8_15 74 I/O
(unused) 0 0 0 5 FB8_16 (b)
(unused) 0 0 0 5 FB8_17 75 I/O
(unused) 0 0 0 5 FB8_18 (b)
Signals Used by Logic in Function Block
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
led4 ........................................ 0 0
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
led4 = Gnd;
dout<0>.D = din<0>;
!dout<0>.CLK = rd; // GCK
dout<0>.OE = !(led2.PIN);
led2.D = cs;
!led2.CLK = rd; // GCK
**************************** Device Pin Out ****************************
Device : XC95144-7-PQ100
d
i
n
V < T T T T T T T T V T T T G T T T T T
C 0 I I I I I I I I C I I I N D I I I I
C > E E E E E E E E C E E E D O E E E E
----------------------------------------
/100 98 96 94 92 90 88 86 84 82 \
| 99 97 95 93 91 89 87 85 83 81 |
TIE | 1 80 | TIE
GND | 2 79 | TIE
TIE | 3 78 | TIE
TIE | 4 77 | GND
TIE | 5 76 | TIE
TIE | 6 75 | TIE
VCC | 7 74 | TIE
dout<0> | 8 73 | TIE
TIE | 9 72 | TIE
TIE | 10 71 | GND
TIE | 11 70 | TIE
TIE | 12 69 | TIE
led2 | 13 XC95144-7-PQ100 68 | TIE
TIE | 14 67 | TIE
TIE | 15 66 | cs
TIE | 16 65 | led4
TIE | 17 64 | GND
TIE | 18 63 | TIE
TIE | 19 62 | TIE
TIE | 20 61 | TIE
TIE | 21 60 | TIE
TIE | 22 59 | VCC
GND | 23 58 | TIE
rd | 24 57 | TIE
TIE | 25 56 | TIE
TIE | 26 55 | TIE
TIE | 27 54 | TIE
VCC | 28 53 | VCC
TIE | 29 52 | TIE
TIE | 30 51 | TIE
| 32 34 36 38 40 42 44 46 48 50 |
\31 33 35 37 39 41 43 45 47 49 /
----------------------------------------
T T G T T T T T T V T T T T T G T T T T
I I N I I I I I I C I I I I I N D I M C
E E D E E E E E E C E E E E E D I E S K
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC95144-7-PQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Slew Rate : FAST
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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