regdd.vhd

来自「此文件是对xilinx95144器件编的程序」· VHDL 代码 · 共 28 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity regdd is
    Port (cs,rd: in std_logic;
	        din: in std_logic;
	 			dout : out std_logic

	 		 );
end regdd;

architecture Behavioral of regdd is
begin


MAIN: process(rd,cs,din)
begin

	if (cs = '0' and rd = '0' )then
	
			dout <= din;
    else 
			dout <= 'Z';
	end if;
end process;

end Behavioral;