regd.tim

此文件是对xilinx95144器件编的程序

                           Performance Summary Report
                           --------------------------

Design:     regd
Device:     XC95144-7-PQ100
Speed File: Version 3.0
Program:    Timing Report Generator:  version F.31
Date:       Wed Aug 11 14:40:38 2004

Performance Summary:

Clock net 'rd' path delays:

Clock Pad to Output Pad (tCO)             :         14.0ns (2 macrocell levels)
Clock Pad 'rd' to Output Pad 'dout<0>'                            (Pterm Clock)

Setup to Clock at the Pad (tSU)           :          4.5ns (0 macrocell levels)
Data signal 'din<0>' to DFF D input Pin at 'dout<0>.D'
Clock pad 'rd'                                                            (GCK)

                          Minimum Clock Period: 8.0ns
                     Maximum Internal Clock Speed: 125.0Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From      r
 \          d
  \          
   \         
    \        
     \       
      \      
  To   \------

dout<0>  14.0
led2      4.5

--------------------------------------------------------------------------------
                   Setup to Clock at Pad (tSU or tSUF) (nsec)

\ From      r
 \          d
  \          
   \         
    \        
     \       
      \      
  To   \------

cs        4.5
din<0>    4.5

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU or tSUF) -     Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and ends at register 
                                          (Fast Input Register for tSUF) D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. Pin-to-pin setup 
                                          requirement is not reported or 
                                          guaranteed for product-term clocks 
                                          derived from macrocell feedback 
                                          signals. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.