d4_16.vhd

此文件是对xilinx95144器件编的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity d4_16 is
    Port ( cs,reset : in std_logic;
			 din: IN std_logic_vector(3 DOWNTO 0);
           cs_out : OUT std_logic_vector(15 downto 0));
end d4_16;

architecture Behavioral of d4_16 is


begin
 
process(reset,cs,din)
begin
 
if  reset = '1' then
  cs_out <= "1111111111111111";
else--if clk'event and clk = '1' then
	if cs = '0' then
   	case din is
      	when "0000" => cs_out <= "1111111111111110";	  --0
      	when "0001" => cs_out <= "1111111111111101";	  --1
      	when "0010" => cs_out <= "1111111111111011";   --2
      	when "0011" => cs_out <= "1111111111110111";	  --3
      	when "0100" => cs_out <= "1111111111101111";	  --4
      	when "0101" => cs_out <= "1111111111011111";	  --5
      	when "0110" => cs_out <= "1111111110111111";	  --6
      	when "0111" => cs_out <= "1111111101111111";	  --7
		when "1000" => cs_out <= "1111111011111111";	  --8
		when "1001" => cs_out <= "1111110111111111";	  --9
      	when "1010" => cs_out <= "1111101111111111";	  --10
		when "1011" => cs_out <= "1111011111111111";	  --11
		when "1100" => cs_out <= "1110111111111111";	  --12
		when "1101" => cs_out <= "1101111111111111";	  --13
		when "1110" => cs_out <= "1011111111111111";	  --14
		when "1111" => cs_out <= "0111111111111111";	  --15
		when others => cs_out <= "1111111111111111";
   	end case;
	else
		 cs_out <= "1111111111111111";
	end if;
end if;
end process; 
end Behavioral;