regd.vhd

来自「此文件是对xilinx95144器件编的程序」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity regd is
    generic (size:integer:=1);
    Port (cs,rd: in std_logic;
	        din: in std_logic_vector(size-1 downto 0);
	 			dout : out std_logic_vector(size-1 downto 0)
		

	 		 );
end regd;

architecture Behavioral of regd is
begin



MAIN: process(rd,cs,din)
begin
	if ( cs = '0' and rd = '0')then
      
			dout <= din;
     else 
		   
			dout <=(others => 'Z');
		
	end if;
end process;

end Behavioral;