reg2_4.vhd

此文件是对xilinx95144器件编的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg2_4 is
    Port ( cs,wr,reset : in std_logic;       
			 din: IN std_logic_vector(2 downto 0);
           dout : out std_logic_vector(3 downto 0)
			 -- led : out std_logic_vector(2 downto 0)
			 );
end reg2_4;
architecture Behavioral of reg2_4 is
	signal  indata:std_logic_vector(1 downto 0);
	begin
 		indata<=din(1)&din(0);
		process(cs,wr,reset)
		begin
			if  reset='1' then
		    		dout<="1111";
			elsif cs = '0' then
				if(wr'event and wr = '0') then
					if(din(2) = '1') then
						dout <= "1111";
					elsif(din(2) = '0') then
						case indata is
							when "00" => dout <= "1110";	  --0
                       			when "01" => dout <= "1101";	  --1
                       			when "10" => dout <= "1011";    --2
                       			when "11" => dout <= "0111";	  --3
	    	              			when others => dout<="1111";
                    		end case;
					 end if;
				end if;
			end if;
  		 end process;
end Behavioral;