📄 tba_2472.rpt
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outputl<1>.CLK = !(wr);
outputl<1>.AP = reset; // GSR
outputl<2>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
p0<2>.PIN & !(inter_add<2>) & inter_add<3> &
!(outputl_2_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(p0<2>.PIN) & !(inter_add<2>) & inter_add<3> &
outputl_2_obuf.FBK.LFBK;
outputl<2>.CLK = !(wr);
outputl<2>.AP = reset; // GSR
outputl<3>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & p0<3>.PIN & inter_add<3> &
!(outputl_3_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & !(p0<3>.PIN) & inter_add<3> &
outputl_3_obuf.FBK.LFBK;
outputl<3>.CLK = !(wr);
outputl<3>.AP = reset; // GSR
outputl<4>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & p0<4>.PIN &
!(outputl_4_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & !(p0<4>.PIN) &
outputl_4_obuf.FBK.LFBK;
outputl<4>.CLK = !(wr);
outputl<4>.AP = reset; // GSR
outputl<5>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & p0<5>.PIN &
!(outputl_5_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & !(p0<5>.PIN) &
outputl_5_obuf.FBK.LFBK;
outputl<5>.CLK = !(wr);
outputl<5>.AP = reset; // GSR
outputl<6>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & p0<6> & !(outputl_6_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & !(p0<6>) & outputl_6_obuf.FBK.LFBK;
outputl<6>.CLK = !(wr);
outputl<6>.AP = reset; // GSR
outputl<7>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & p0<7> & !(outputl_7_obuf.FBK.LFBK)
# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & inter_add<3> & !(p0<7>) & outputl_7_obuf.FBK.LFBK;
outputl<7>.CLK = !(wr);
outputl<7>.AP = reset; // GSR
p0_0_iobufe = p0_0_iobufe$WA0 & p0_0_iobufe$WA1 &
p0_0_iobufe$WA2 & p0_0_iobufe$WA3 & p0_0_iobufe$WA4; FC node
p0<0> = p0_0_iobufe;
p0<0>.OE = !(cs) & !(reset) & !(inter_add<3>) & !(rd) &
$OpTx$FX_DC$11;
p0_0_iobufe$WA0 = playing;
p0_0_iobufe$WA0.OE = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) &
!(inter_add<2>) & !(inter_add<3>) & !(rd);
p0_0_iobufe$WA1 = speed<0>;
p0_0_iobufe$WA1.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
inter_add<2> & !(inter_add<3>) & !(rd);
p0_0_iobufe$WA2 = m_s_in;
p0_0_iobufe$WA2.OE = !(cs) & !(reset) & inter_add<0> & inter_add<1> &
!(inter_add<2>) & !(inter_add<3>) & !(rd);
p0_0_iobufe$WA3 = radio;
p0_0_iobufe$WA3.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
!(inter_add<2>) & !(inter_add<3>) & !(rd);
p0_0_iobufe$WA4 = nofile;
p0_0_iobufe$WA4.OE = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) &
!(inter_add<2>) & !(inter_add<3>) & !(rd);
pa_c.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) &
!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & !(pa_c_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) &
!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & pa_c_obuf.FBK.LFBK;
pa_c.CLK = !(wr);
pa_c.AP = reset; // GSR
play_s.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> &
!(inter_add<1>) & inter_add<2> & !(inter_add<3>) &
!(play_s_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> &
!(inter_add<1>) & inter_add<2> & !(inter_add<3>) &
play_s_obuf.FBK.LFBK;
play_s.CLK = !(wr);
play_s.AP = reset; // GSR
!check<0>.D = !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) &
!(p0<1>.PIN) & !(inter_add<1>) & inter_add<2> & inter_add<3>;
check<0>.CLK = !(wr);
check<0>.AP = reset; // GSR
!check<1>.D = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) &
!(p0<1>.PIN) & !(inter_add<1>) & inter_add<2> & inter_add<3>;
check<1>.CLK = !(wr);
check<1>.AP = reset; // GSR
!check<2>.D = !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) &
p0<1>.PIN & !(inter_add<1>) & inter_add<2> & inter_add<3>;
check<2>.CLK = !(wr);
check<2>.AP = reset; // GSR
p0<1> = speed<1>;
p0<1>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
inter_add<2> & !(inter_add<3>) & !(rd);
p0<2> = speed<2>;
p0<2>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
inter_add<2> & !(inter_add<3>) & !(rd);
p0<3> = speed<3>;
p0<3>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
inter_add<2> & !(inter_add<3>) & !(rd);
p0<4> = speed<4>;
p0<4>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
inter_add<2> & !(inter_add<3>) & !(rd);
p0<5> = speed<5>;
p0<5>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> &
inter_add<2> & !(inter_add<3>) & !(rd);
stop_s.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) &
inter_add<1> & inter_add<2> & !(inter_add<3>) &
!(stop_s_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) &
inter_add<1> & inter_add<2> & !(inter_add<3>) &
stop_s_obuf.FBK.LFBK;
stop_s.CLK = !(wr);
stop_s.AP = reset; // GSR
updown.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> &
inter_add<1> & !(inter_add<2>) & !(inter_add<3>) &
!(updown_obuf.FBK.LFBK)
# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> &
inter_add<1> & !(inter_add<2>) & !(inter_add<3>) &
updown_obuf.FBK.LFBK;
updown.CLK = !(wr);
updown.AP = reset; // GSR
**************************** Device Pin Out ****************************
Device : XC95144-7-PQ100
l l l l
e e e e l l l l
e d d d d e e e e
n d d d d l d d d d l
V T T T T T 4 < < < V < e < G T < < < o
C I I I I I 8 3 2 1 C 0 d 2 N D 3 4 5 a
C E E E E E 5 > > > C > 1 > D O > > > d
----------------------------------------
/100 98 96 94 92 90 88 86 84 82 \
| 99 97 95 93 91 89 87 85 83 81 |
reset | 1 80 | TIE
GND | 2 79 | TIE
ale | 3 78 | TIE
TIE | 4 77 | GND
cs | 5 76 | TIE
TIE | 6 75 | outputl<0>
VCC | 7 74 | outputl<1>
TIE | 8 73 | outputl<2>
TIE | 9 72 | outputl<3>
TIE | 10 71 | GND
TIE | 11 70 | outputl<4>
TIE | 12 69 | outputl<5>
p0<0> | 13 XC95144-7-PQ100 68 | outputl<6>
p0<1> | 14 67 | outputl<7>
p0<2> | 15 66 | outputh<8>
p0<3> | 16 65 | outputh<9>
p0<4> | 17 64 | GND
p0<5> | 18 63 | updown
p0<6> | 19 62 | check<0>
p0<7> | 20 61 | playing
wr | 21 60 | nofile
rd | 22 59 | VCC
GND | 23 58 | check<1>
TIE | 24 57 | check<2>
TIE | 25 56 | lcd_c
TIE | 26 55 | radio
TIE | 27 54 | play_s
VCC | 28 53 | VCC
TIE | 29 52 | stop_s
TIE | 30 51 | speed<0>
| 32 34 36 38 40 42 44 46 48 50 |
\31 33 35 37 39 41 43 45 47 49 /
----------------------------------------
T T G T T T T p m V m s s s s G T s T T
I I N I I I I a _ C _ p p p p N D p M C
E E D E E E E _ s C s e e e e D I e S K
c _ _ e e e e e
o i d d d d d
u n < < < < <
t 5 4 3 2 1
> > > > >
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC95144-7-PQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Slew Rate : FAST
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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