fir.map.rpt

自己在一个通信项目中设计的滤波器

Analysis & Synthesis report for FIR
Tue Dec 26 15:26:36 2006
Version 4.0 Build 190 1/28/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Analysis & Synthesis Files Read
  6. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------+
; Analysis & Synthesis Summary                                    ;
+-----------------------------+-----------------------------------+
; Analysis & Synthesis Status ; Failed - Tue Dec 26 15:26:36 2006 ;
; Revision Name               ; FIR                               ;
; Top-level Entity Name       ; FIR                               ;
; Family                      ; Cyclone                           ;
+-----------------------------+-----------------------------------+


+----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                          ;
+-----------------------------------------------------------------------------------------
; Option                                                  ; Setting      ; Default Value ;
+---------------------------------------------------------+--------------+---------------+
; Top-level entity name                                   ; FIR          ;               ;
; Family name                                             ; Cyclone      ; Stratix       ;
; Auto Resource Sharing                                   ; Off          ; Off           ;
; Auto Shift Register Replacement                         ; On           ; On            ;
; Auto RAM Replacement                                    ; On           ; On            ;
; Auto ROM Replacement                                    ; On           ; On            ;
; Allow register retiming to trade off Tsu/Tco with Fmax  ; On           ; On            ;
; Perform gate-level register retiming                    ; Off          ; Off           ;
; Perform WYSIWYG Primitive Resynthesis                   ; Off          ; Off           ;
; Remove Duplicate Logic                                  ; On           ; On            ;
; Auto Open-Drain Pins                                    ; On           ; On            ;
; Auto Carry Chains                                       ; On           ; On            ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II ; 70           ; 70            ;
; Optimization Technique -- Cyclone                       ; Balanced     ; Balanced      ;
; Auto Global Register Control Signals                    ; On           ; On            ;
; Auto Global Clock                                       ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                          ; Off          ; Off           ;
; Ignore SOFT Buffers                                     ; On           ; On            ;
; Ignore LCELL Buffers                                    ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                               ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                   ; Off          ; Off           ;
; Ignore CASCADE Buffers                                  ; Off          ; Off           ;
; Ignore CARRY Buffers                                    ; Off          ; Off           ;
; Remove Duplicate Registers                              ; On           ; On            ;
; Remove Redundant Logic Cells                            ; Off          ; Off           ;
; Power-Up Don't Care                                     ; On           ; On            ;
; NOT Gate Push-Back                                      ; On           ; On            ;
; State Machine Processing                                ; Auto         ; Auto          ;
; VHDL Version                                            ; VHDL93       ; VHDL93        ;
; Verilog Version                                         ; Verilog_2001 ; Verilog_2001  ;
; Preserve fewer node names                               ; On           ; On            ;
; Disk space/compilation speed tradeoff                   ; Normal       ; Normal        ;
; Create Debugging Nodes for IP Cores                     ; off          ; off           ;
+---------------------------------------------------------+--------------+---------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name               ; Setting                    ;
+--------------------+----------------------------+
; CARRY_CHAIN        ; MANUAL                     ;
; CASCADE_CHAIN      ; MANUAL                     ;
; OPTIMIZE_FOR_SPEED ; 5                          ;
; STYLE              ; FAST                       ;
+--------------------+----------------------------+


+---------------------------------+
; Analysis & Synthesis Files Read ;
+----------------------------------
; File Name ; Read                ;
+-----------+---------------------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Tue Dec 26 15:26:27 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off FIR -c FIR
Error: VHDL Use Clause error at FIR.VHD(4): design library work does not contain primary unit signed_arith
Error: VHDL Use Clause error at FIR.VHD(5): design library work does not contain primary unit coeffs
Error: Ignored construct fir at FIR.VHD(7) because of previous errors
Error: VHDL error at FIR.VHD(13): entity fir is used but not declared
Error: VHDL error at FIR.VHD(17): object signed is used but not declared
Error: VHDL error at FIR.VHD(18): object signed is used but not declared
Error: VHDL error at FIR.VHD(19): object signed is used but not declared
Error: VHDL error at FIR.VHD(24): object cannot be indexed because it has shift_arr type rather than array type
Error: VHDL error at FIR.VHD(26): object result is used but not declared
Error: VHDL error at FIR.VHD(27): object clk is used but not declared
Error: VHDL error at FIR.VHD(28): object reset is used but not declared
Error: VHDL error at FIR.VHD(31): object tmp is used but not declared
Error: VHDL error at FIR.VHD(32): object pro is used but not declared
Error: VHDL error at FIR.VHD(33): object acc is used but not declared
Error: VHDL error at FIR.VHD(35): object old is used but not declared
Error: VHDL error at FIR.VHD(36): object pro is used but not declared
Error: VHDL error at FIR.VHD(37): object acc is used but not declared
Error: VHDL error at FIR.VHD(38): object cannot be indexed because it has shift_arr type rather than array type
Error: VHDL error at FIR.VHD(40): object cannot be indexed because it has shift_arr type rather than array type
Info: Found 0 design units and 0 entities in source file FIR.VHD
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
    Error: Processing ended: Tue Dec 26 15:26:35 2006
    Error: Elapsed time: 00:00:07