songer.tan.qmsg

基于FPGA的乐曲硬件演奏电路设计的实现

{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|CODE\[2\]~458 " "Warning: Node ToneTaba:u2\|CODE\[2\]~458 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 5 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|CODE\[1\]~459 " "Warning: Node ToneTaba:u2\|CODE\[1\]~459 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 5 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|CODE\[0\]~460 " "Warning: Node ToneTaba:u2\|CODE\[0\]~460 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 5 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|HIGH~27 " "Warning: Node ToneTaba:u2\|HIGH~27 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 6 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[0\]~302 " "Warning: Node ToneTaba:u2\|Tone\[0\]~302 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[1\]~303 " "Warning: Node ToneTaba:u2\|Tone\[1\]~303 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[2\]~304 " "Warning: Node ToneTaba:u2\|Tone\[2\]~304 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[3\]~305 " "Warning: Node ToneTaba:u2\|Tone\[3\]~305 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[4\]~306 " "Warning: Node ToneTaba:u2\|Tone\[4\]~306 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[5\]~307 " "Warning: Node ToneTaba:u2\|Tone\[5\]~307 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[6\]~308 " "Warning: Node ToneTaba:u2\|Tone\[6\]~308 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[7\]~309 " "Warning: Node ToneTaba:u2\|Tone\[7\]~309 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[9\]~310 " "Warning: Node ToneTaba:u2\|Tone\[9\]~310 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[8\]~312 " "Warning: Node ToneTaba:u2\|Tone\[8\]~312 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ToneTaba:u2\|Tone\[10\]~311 " "Warning: Node ToneTaba:u2\|Tone\[10\]~311 is a latch" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node altera_internal_jtag~TCKUTAP is an undefined clock" {  } { { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK8HZ " "Info: Assuming node CLK8HZ is an undefined clock" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 5 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK8HZ" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK12MHZ " "Info: Assuming node CLK12MHZ is an undefined clock" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 4 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK12MHZ" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[2\] " "Info: Detected ripple clock Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[2\] as buffer" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" 76 8 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[3\] " "Info: Detected ripple clock Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[3\] as buffer" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" 76 8 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[3\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "Speakera:u3\|PreCLK~15 " "Info: Detected gated clock Speakera:u3\|PreCLK~15 as buffer" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" 10 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "Speakera:u3\|PreCLK~15" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "Speakera:u3\|FullSpkS " "Info: Detected ripple clock Speakera:u3\|FullSpkS as buffer" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" 23 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "Speakera:u3\|FullSpkS" } } } }  } 0}  } {  } 0}