songer.map.rpt

基于FPGA的乐曲硬件演奏电路设计的实现

; e:/altera/quartus41/libraries/megafunctions/declut.inc                           ; yes             ;
; H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/decode_9ie.tdf      ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd                        ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf                      ; yes             ;
; H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ia7.tdf        ; yes             ;
; H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf        ; yes             ;
; H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf        ; yes             ;
; H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_v98.tdf        ; yes             ;
+----------------------------------------------------------------------------------+-----------------+


+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                  ;
+-----------------------------------+--------------------------+
; Resource                          ; Usage                    ;
+-----------------------------------+--------------------------+
; Logic cells                       ; 232                      ;
; Total combinational functions     ; 198                      ;
; Total 4-input functions           ; 73                       ;
; Total 3-input functions           ; 63                       ;
; Total 2-input functions           ; 21                       ;
; Total 1-input functions           ; 41                       ;
; Total 0-input functions           ; 0                        ;
; Combinational cells for routing   ; 0                        ;
; Total registers                   ; 125                      ;
; Total logic cells in carry chains ; 41                       ;
; I/O pins                          ; 8                        ;
; Total memory bits                 ; 1024                     ;
; Maximum fan-out node              ; altera_internal_jtag~TDO ;
; Maximum fan-out                   ; 111                      ;
; Total fan-out                     ; 1030                     ;
; Average fan-out                   ; 4.14                     ;
+-----------------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                 ;
+---------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+-----------+
; Name                                                                                                                      ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF       ;
+---------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+-----------+
; NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 256          ; 4            ; 256          ; 4            ; 1024 ; data1.mif ;
+---------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+-----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Sep 07 14:09:25 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off SONGER -c SONGER
Info: Found 2 design units, including 1 entities, in source file music.vhd
    Info: Found design unit 1: music-SYN
    Info: Found entity 1: music
Info: Found 2 design units, including 1 entities, in source file notetabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Info: Found 2 design units, including 1 entities, in source file SONGER.vhd
    Info: Found design unit 1: Songer-one
    Info: Found entity 1: Songer
Info: Found 2 design units, including 1 entities, in source file speakera.vhd
    Info: Found design unit 1: Speakera-one
    Info: Found entity 1: Speakera
Info: Found 2 design units, including 1 entities, in source file tonetaba.vhd
    Info: Found design unit 1: ToneTaba-one
    Info: Found entity 1: ToneTaba
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_des.tdf
    Info: Found entity 1: altsyncram_des
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_j6a2.tdf
    Info: Found entity 1: altsyncram_j6a2
Info: Found 3 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable tone may not be assigned a new value in every possible path through the Process Statement. Signal or variable tone holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable code may not be assigned a new value in every possible path through the Process Statement. Signal or variable code holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable high may not be assigned a new value in every possible path through the Process Statement. Signal or variable high holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 6 design units, including 2 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf
    Info: Found entity 1: decode_9ie
Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Ignored 16 buffer(s)
    Info: Ignored 16 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register Speakera:u3|SpkS merged to single register Speakera:u3|\DelaySpkS:Count2
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: NoteTabs:u1|Counter[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: Speakera:u3|\GenSpkS:Count11[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: Speakera:u3|\DivideCLK:Count4[0]~0
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~320
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_ia7.tdf
    Info: Found entity 1: cntr_ia7
Info: Found 1 design units, including 1 entities, in source file db/cntr_7t7.tdf
    Info: Found entity 1: cntr_7t7
Info: Found 1 design units, including 1 entities, in source file db/cntr_ea7.tdf
    Info: Found entity 1: cntr_ea7
Info: Found 1 design units, including 1 entities, in source file db/cntr_v98.tdf
    Info: Found entity 1: cntr_v98
Warning: Output pins are stuck at VCC or GND
    Warning: Pin CODE1[3] stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 249 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 7 output pins
    Info: Implemented 232 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Wed Sep 07 14:09:41 2005
    Info: Elapsed time: 00:00:15