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📄 songer.fit.eqn

📁 基于FPGA的乐曲硬件演奏电路设计的实现
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--E1_\DelaySpkS:Count2 is Speakera:u3|\DelaySpkS:Count2 at LC_X5_Y9_N7
--operation mode is normal

E1_\DelaySpkS:Count2_lut_out = !E1_\DelaySpkS:Count2;
E1_\DelaySpkS:Count2 = DFFEA(E1_\DelaySpkS:Count2_lut_out, E1_FullSpkS, VCC, , , , );


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y6_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L61Q);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y6_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L61Q);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y6_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L61Q);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y6_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L61Q);


--S1_q_a[2] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_a[2] at M4K_X13_Y4
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 256, Port B Width: 4
--Port A Logical Depth: 256, Port A Logical Width: 4, Port B Logical Depth: 256, Port B Logical Width: 4
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S1_q_a[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[2]_PORT_A_data_in_reg = DFFE(S1_q_a[2]_PORT_A_data_in, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_a[2]_PORT_B_data_in_reg = DFFE(S1_q_a[2]_PORT_B_data_in, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_a[2]_PORT_A_address_reg = DFFE(S1_q_a[2]_PORT_A_address, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_a[2]_PORT_B_address_reg = DFFE(S1_q_a[2]_PORT_B_address, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_write_enable = GND;
S1_q_a[2]_PORT_A_write_enable_reg = DFFE(S1_q_a[2]_PORT_A_write_enable, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_write_enable = T1L13;
S1_q_a[2]_PORT_B_write_enable_reg = DFFE(S1_q_a[2]_PORT_B_write_enable, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_a[2]_clock_1 = GLOBAL(A1L5);
S1_q_a[2]_PORT_A_data_out = MEMORY(S1_q_a[2]_PORT_A_data_in_reg, S1_q_a[2]_PORT_B_data_in_reg, S1_q_a[2]_PORT_A_address_reg, S1_q_a[2]_PORT_B_address_reg, S1_q_a[2]_PORT_A_write_enable_reg, S1_q_a[2]_PORT_B_write_enable_reg, , , S1_q_a[2]_clock_0, S1_q_a[2]_clock_1, , , , );
S1_q_a[2] = S1_q_a[2]_PORT_A_data_out[0];

--S1_q_b[2] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_b[2] at M4K_X13_Y4
S1_q_b[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[2]_PORT_A_data_in_reg = DFFE(S1_q_b[2]_PORT_A_data_in, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_b[2]_PORT_B_data_in_reg = DFFE(S1_q_b[2]_PORT_B_data_in, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_b[2]_PORT_A_address_reg = DFFE(S1_q_b[2]_PORT_A_address, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_b[2]_PORT_B_address_reg = DFFE(S1_q_b[2]_PORT_B_address, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_write_enable = GND;
S1_q_b[2]_PORT_A_write_enable_reg = DFFE(S1_q_b[2]_PORT_A_write_enable, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_write_enable = T1L13;
S1_q_b[2]_PORT_B_write_enable_reg = DFFE(S1_q_b[2]_PORT_B_write_enable, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_b[2]_clock_1 = GLOBAL(A1L5);
S1_q_b[2]_PORT_B_data_out = MEMORY(S1_q_b[2]_PORT_A_data_in_reg, S1_q_b[2]_PORT_B_data_in_reg, S1_q_b[2]_PORT_A_address_reg, S1_q_b[2]_PORT_B_address_reg, S1_q_b[2]_PORT_A_write_enable_reg, S1_q_b[2]_PORT_B_write_enable_reg, , , S1_q_b[2]_clock_0, S1_q_b[2]_clock_1, , , , );
S1_q_b[2] = S1_q_b[2]_PORT_B_data_out[0];

--S1_q_a[0] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_a[0] at M4K_X13_Y4
S1_q_a[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[2]_PORT_A_data_in_reg = DFFE(S1_q_a[2]_PORT_A_data_in, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_a[2]_PORT_B_data_in_reg = DFFE(S1_q_a[2]_PORT_B_data_in, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_a[2]_PORT_A_address_reg = DFFE(S1_q_a[2]_PORT_A_address, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_a[2]_PORT_B_address_reg = DFFE(S1_q_a[2]_PORT_B_address, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_write_enable = GND;
S1_q_a[2]_PORT_A_write_enable_reg = DFFE(S1_q_a[2]_PORT_A_write_enable, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_write_enable = T1L13;
S1_q_a[2]_PORT_B_write_enable_reg = DFFE(S1_q_a[2]_PORT_B_write_enable, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_a[2]_clock_1 = GLOBAL(A1L5);
S1_q_a[2]_PORT_A_data_out = MEMORY(S1_q_a[2]_PORT_A_data_in_reg, S1_q_a[2]_PORT_B_data_in_reg, S1_q_a[2]_PORT_A_address_reg, S1_q_a[2]_PORT_B_address_reg, S1_q_a[2]_PORT_A_write_enable_reg, S1_q_a[2]_PORT_B_write_enable_reg, , , S1_q_a[2]_clock_0, S1_q_a[2]_clock_1, , , , );
S1_q_a[0] = S1_q_a[2]_PORT_A_data_out[3];

--S1_q_a[3] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_a[3] at M4K_X13_Y4
S1_q_a[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[2]_PORT_A_data_in_reg = DFFE(S1_q_a[2]_PORT_A_data_in, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_a[2]_PORT_B_data_in_reg = DFFE(S1_q_a[2]_PORT_B_data_in, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_a[2]_PORT_A_address_reg = DFFE(S1_q_a[2]_PORT_A_address, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_a[2]_PORT_B_address_reg = DFFE(S1_q_a[2]_PORT_B_address, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_write_enable = GND;
S1_q_a[2]_PORT_A_write_enable_reg = DFFE(S1_q_a[2]_PORT_A_write_enable, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_write_enable = T1L13;
S1_q_a[2]_PORT_B_write_enable_reg = DFFE(S1_q_a[2]_PORT_B_write_enable, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_a[2]_clock_1 = GLOBAL(A1L5);
S1_q_a[2]_PORT_A_data_out = MEMORY(S1_q_a[2]_PORT_A_data_in_reg, S1_q_a[2]_PORT_B_data_in_reg, S1_q_a[2]_PORT_A_address_reg, S1_q_a[2]_PORT_B_address_reg, S1_q_a[2]_PORT_A_write_enable_reg, S1_q_a[2]_PORT_B_write_enable_reg, , , S1_q_a[2]_clock_0, S1_q_a[2]_clock_1, , , , );
S1_q_a[3] = S1_q_a[2]_PORT_A_data_out[2];

--S1_q_a[1] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_a[1] at M4K_X13_Y4
S1_q_a[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[2]_PORT_A_data_in_reg = DFFE(S1_q_a[2]_PORT_A_data_in, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_a[2]_PORT_B_data_in_reg = DFFE(S1_q_a[2]_PORT_B_data_in, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_a[2]_PORT_A_address_reg = DFFE(S1_q_a[2]_PORT_A_address, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_a[2]_PORT_B_address_reg = DFFE(S1_q_a[2]_PORT_B_address, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_write_enable = GND;
S1_q_a[2]_PORT_A_write_enable_reg = DFFE(S1_q_a[2]_PORT_A_write_enable, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_write_enable = T1L13;
S1_q_a[2]_PORT_B_write_enable_reg = DFFE(S1_q_a[2]_PORT_B_write_enable, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_a[2]_clock_1 = GLOBAL(A1L5);
S1_q_a[2]_PORT_A_data_out = MEMORY(S1_q_a[2]_PORT_A_data_in_reg, S1_q_a[2]_PORT_B_data_in_reg, S1_q_a[2]_PORT_A_address_reg, S1_q_a[2]_PORT_B_address_reg, S1_q_a[2]_PORT_A_write_enable_reg, S1_q_a[2]_PORT_B_write_enable_reg, , , S1_q_a[2]_clock_0, S1_q_a[2]_clock_1, , , , );
S1_q_a[1] = S1_q_a[2]_PORT_A_data_out[1];

--S1_q_b[0] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_b[0] at M4K_X13_Y4
S1_q_b[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[2]_PORT_A_data_in_reg = DFFE(S1_q_b[2]_PORT_A_data_in, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_b[2]_PORT_B_data_in_reg = DFFE(S1_q_b[2]_PORT_B_data_in, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_b[2]_PORT_A_address_reg = DFFE(S1_q_b[2]_PORT_A_address, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_b[2]_PORT_B_address_reg = DFFE(S1_q_b[2]_PORT_B_address, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_write_enable = GND;
S1_q_b[2]_PORT_A_write_enable_reg = DFFE(S1_q_b[2]_PORT_A_write_enable, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_write_enable = T1L13;
S1_q_b[2]_PORT_B_write_enable_reg = DFFE(S1_q_b[2]_PORT_B_write_enable, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_b[2]_clock_1 = GLOBAL(A1L5);
S1_q_b[2]_PORT_B_data_out = MEMORY(S1_q_b[2]_PORT_A_data_in_reg, S1_q_b[2]_PORT_B_data_in_reg, S1_q_b[2]_PORT_A_address_reg, S1_q_b[2]_PORT_B_address_reg, S1_q_b[2]_PORT_A_write_enable_reg, S1_q_b[2]_PORT_B_write_enable_reg, , , S1_q_b[2]_clock_0, S1_q_b[2]_clock_1, , , , );
S1_q_b[0] = S1_q_b[2]_PORT_B_data_out[3];

--S1_q_b[3] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_b[3] at M4K_X13_Y4
S1_q_b[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[2]_PORT_A_data_in_reg = DFFE(S1_q_b[2]_PORT_A_data_in, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_b[2]_PORT_B_data_in_reg = DFFE(S1_q_b[2]_PORT_B_data_in, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_b[2]_PORT_A_address_reg = DFFE(S1_q_b[2]_PORT_A_address, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_b[2]_PORT_B_address_reg = DFFE(S1_q_b[2]_PORT_B_address, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_write_enable = GND;
S1_q_b[2]_PORT_A_write_enable_reg = DFFE(S1_q_b[2]_PORT_A_write_enable, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_write_enable = T1L13;
S1_q_b[2]_PORT_B_write_enable_reg = DFFE(S1_q_b[2]_PORT_B_write_enable, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_b[2]_clock_1 = GLOBAL(A1L5);
S1_q_b[2]_PORT_B_data_out = MEMORY(S1_q_b[2]_PORT_A_data_in_reg, S1_q_b[2]_PORT_B_data_in_reg, S1_q_b[2]_PORT_A_address_reg, S1_q_b[2]_PORT_B_address_reg, S1_q_b[2]_PORT_A_write_enable_reg, S1_q_b[2]_PORT_B_write_enable_reg, , , S1_q_b[2]_clock_0, S1_q_b[2]_clock_1, , , , );
S1_q_b[3] = S1_q_b[2]_PORT_B_data_out[2];

--S1_q_b[1] is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_b[1] at M4K_X13_Y4
S1_q_b[2]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[2]_PORT_A_data_in_reg = DFFE(S1_q_b[2]_PORT_A_data_in, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[1], T1_ram_rom_data_reg[3], T1_ram_rom_data_reg[0]);
S1_q_b[2]_PORT_B_data_in_reg = DFFE(S1_q_b[2]_PORT_B_data_in, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7]);
S1_q_b[2]_PORT_A_address_reg = DFFE(S1_q_b[2]_PORT_A_address, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_address = BUS(U1_safe_q[0], U1_safe_q[1], U1_safe_q[2], U1_safe_q[3], U1_safe_q[4], U1_safe_q[5], U1_safe_q[6], U1_safe_q[7]);
S1_q_b[2]_PORT_B_address_reg = DFFE(S1_q_b[2]_PORT_B_address, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_write_enable = GND;
S1_q_b[2]_PORT_A_write_enable_reg = DFFE(S1_q_b[2]_PORT_A_write_enable, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_write_enable = T1L13;
S1_q_b[2]_PORT_B_write_enable_reg = DFFE(S1_q_b[2]_PORT_B_write_enable, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_clock_0 = GLOBAL(CLK8HZ);
S1_q_b[2]_clock_1 = GLOBAL(A1L5);
S1_q_b[2]_PORT_B_data_out = MEMORY(S1_q_b[2]_PORT_A_data_in_reg, S1_q_b[2]_PORT_B_data_in_reg, S1_q_b[2]_PORT_A_address_reg, S1_q_b[2]_PORT_B_address_reg, S1_q_b[2]_PORT_A_write_enable_reg, S1_q_b[2]_PORT_B_write_enable_reg, , , S1_q_b[2]_clock_0, S1_q_b[2]_clock_1, , , , );
S1_q_b[1] = S1_q_b[2]_PORT_B_data_out[1];


--D1L7 is ToneTaba:u2|CODE[2]~461 at LC_X8_Y8_N1
--operation mode is normal

D1L7 = !S1_q_a[1] # !S1_q_a[3];


--D1L11 is ToneTaba:u2|Mux~121 at LC_X5_Y4_N9
--operation mode is normal

D1L11 = S1_q_a[0] & S1_q_a[3] & S1_q_a[1] & !S1_q_a[2] # !S1_q_a[0] & S1_q_a[2] & (S1_q_a[3] $ !S1_q_a[1]);


--D1L6 is ToneTaba:u2|CODE[2]~458 at LC_X8_Y8_N2
--operation mode is normal

D1L6 = LCELL(D1L11 & D1L6 # !D1L11 & S1_q_a[2] & D1L7);


--D1L22 is ToneTaba:u2|Mux~166 at LC_X5_Y4_N6
--operation mode is normal

D1L22 = S1_q_a[0] & S1_q_a[3];


--D1L4 is ToneTaba:u2|CODE[1]~459 at LC_X5_Y4_N3
--operation mode is normal

D1L4 = LCELL(D1L11 & D1L4 # !D1L11 & (S1_q_a[1] $ D1L22));


--D1L1 is ToneTaba:u2|CODE[0]~454 at LC_X5_Y4_N0
--operation mode is normal

D1L1 = S1_q_a[0] & (S1_q_a[1] # !S1_q_a[3]) # !S1_q_a[0] & S1_q_a[3];


--D1L3 is ToneTaba:u2|CODE[0]~460 at LC_X5_Y4_N1
--operation mode is normal

D1L3 = LCELL(D1L1 & (D1L3 # !D1L11) # !D1L1 & D1L11 & D1L3);


--D1L9 is ToneTaba:u2|HIGH~27 at LC_X5_Y10_N3
--operation mode is normal

D1L9 = LCELL(D1L11 & D1L9 # !D1L11 & S1_q_a[3]);


--B1L61Q is sld_hub:sld_hub_inst|HUB_TDO~reg0 at LC_X12_Y6_N9
--operation mode is normal

B1L61Q = AMPP_FUNCTION(!A1L5, F5_Q[0], B1L21, B1L41, !K1_state[8], B1L03);


--T1_ram_rom_incr_write_addr_reg is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg at LC_X10_Y6_N8
--operation mode is normal

T1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L5, T1_ram_rom_load_read_data, VCC);


--F1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X10_Y6_N4
--operation mode is normal

F1_Q[2] = AMPP_FUNCTION(A1L5, F2_Q[2], F6_Q[2], F3_Q[0], !B1L2, B1L02);


--T1L13 is NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1 at LC_X11_Y6_N4
--operation mode is normal

T1L13 = AMPP_FUNCTION(T1_ram_rom_incr_write_addr_reg, F1_Q[2]);


--P1_safe_q[0] is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[0] at LC_X12_Y4_N0
--operation mode is arithmetic

P1_safe_q[0]_lut_out = !P1_safe_q[0];
P1_safe_q[0] = DFFEA(P1_safe_q[0]_lut_out, GLOBAL(CLK8HZ), !C1L1, , , , );

--P1L81 is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[0]~COUT0 at LC_X12_Y4_N0
--operation mode is arithmetic

P1L81_cout_0 = P1_safe_q[0];
P1L81 = CARRY(P1L81_cout_0);

--P1L91 is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[0]~COUT1 at LC_X12_Y4_N0
--operation mode is arithmetic

P1L91_cout_1 = P1_safe_q[0];
P1L91 = CARRY(P1L91_cout_1);


--P1_safe_q[1] is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[1] at LC_X12_Y4_N1
--operation mode is arithmetic

P1_safe_q[1]_lut_out = P1_safe_q[1] $ P1L81;
P1_safe_q[1] = DFFEA(P1_safe_q[1]_lut_out, GLOBAL(CLK8HZ), !C1L1, , , , );

--P1L12 is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[1]~COUT0 at LC_X12_Y4_N1
--operation mode is arithmetic

P1L12_cout_0 = !P1L81 # !P1_safe_q[1];
P1L12 = CARRY(P1L12_cout_0);

--P1L22 is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[1]~COUT1 at LC_X12_Y4_N1
--operation mode is arithmetic

P1L22_cout_1 = !P1L91 # !P1_safe_q[1];
P1L22 = CARRY(P1L22_cout_1);


--P1_safe_q[2] is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[2] at LC_X12_Y4_N2
--operation mode is arithmetic

P1_safe_q[2]_lut_out = P1_safe_q[2] $ !P1L12;
P1_safe_q[2] = DFFEA(P1_safe_q[2]_lut_out, GLOBAL(CLK8HZ), !C1L1, , , , );

--P1L42 is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[2]~COUT0 at LC_X12_Y4_N2
--operation mode is arithmetic

P1L42_cout_0 = P1_safe_q[2] & !P1L12;
P1L42 = CARRY(P1L42_cout_0);

--P1L52 is NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[2]~COUT1 at LC_X12_Y4_N2
--operation mode is arithmetic
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