myc6202.h

基于TMS320C6711的flash烧写程序

/*----------------------------------------------------*/
/*		      Define C6202 registers,etc.             */
/*        Cui Yingwei   Jan 24,2002    Ver 1.0        */
/*----------------------------------------------------*/

#define		CPUPeriod							7

#define		BOOL								unsigned char
#define		TRUE								1
#define		FALSE								0

/*==========================Define EMIF Registers=========================*/
#define		EMIF_GCTL					*(volatile unsigned int*)0x01800000
#define		EMIF_CE0					*(volatile unsigned int*)0x01800008
#define		EMIF_CE1					*(volatile unsigned int*)0x01800004
#define		EMIF_CE2					*(volatile unsigned int*)0x01800010
#define		EMIF_CE3					*(volatile unsigned int*)0x01800014
#define		EMIF_SDRAMCTL				*(volatile unsigned int*)0x01800018
#define		EMIF_SDRAMREF				*(volatile unsigned int*)0x0180001c
/*========================================================================*/

/*==============Define EVM Board Default EMIF Register Values=============*/
#define		DEFAULT_EVM_EMIF_GCTRL				0x00003060
#define 	DEFAULT_EVM_EMIF_CE0_CTRL			0x00000040
#define 	DEFAULT_EVM_EMIF_CE1_CTRL			0x40F40323
#define 	DEFAULT_EVM_EMIF_CE2_CTRL			0x00000030
#define 	DEFAULT_EVM_EMIF_CE3_CTRL			0x00000030
#define 	DEFAULT_EVM_EMIF_SDRAM_CTRL			0x07227000
#define 	DEFAULT_EVM_EMIF_SDRAM_REF			0x4e1
/*========================================================================*/

/*=====================Define CE Space Base Address=======================*/
#define		PRamMap0BaseAddr					0x01400000
			/*Length is 256K(byte), Last Address is 0x0143ffff*/
#define		PRamMap1BaseAddr					0x00000000
			/*Length is 256K(byte), Last Address is 0x003fffff*/
#define		DRamBaseAddr						0x80000000
			/*Length is 128K(byte), Last Address is 0x8001ffff*/
#define		CE0Map0BaseAddr						0x00000000
#define		CE0Map1BaseAddr						0x00400000
#define		CE1Map0BaseAddr						0x01000000
#define		CE1Map1BaseAddr						0x01400002
#define		CE2BaseAddr							0x02000000
#define		CE3BaseAddr							0x03000000
/*========================================================================*/

/*=========================Define UART1 Registers==========================*/
#define		Uart1RBR						*(volatile unsigned char*)0x00440000
#define		Uart1THR						*(volatile unsigned char*)0x00440000
#define		Uart1FCR						*(volatile unsigned char*)0x00440008
#define		Uart1IER						*(volatile unsigned char*)0x00440004
#define		Uart1IIR						*(volatile unsigned char*)0x00440008
#define		Uart1LCR						*(volatile unsigned char*)0x0044000c
#define		Uart1LSR						*(volatile unsigned char*)0x00440014
#define		Uart1MCR						*(volatile unsigned char*)0x00440010
#define		Uart1MSR						*(volatile unsigned char*)0x00440018
#define		Uart1DLL						*(volatile unsigned char*)0x00440000
#define		Uart1DLM						*(volatile unsigned char*)0x00440004
/*========================================================================*/

/*=========================Define UART2 Registers==========================*/
#define		Uart2RBR						*(volatile unsigned char*)0x00480000
#define		Uart2THR						*(volatile unsigned char*)0x00480000
#define		Uart2FCR						*(volatile unsigned char*)0x00480008
#define		Uart2IER						*(volatile unsigned char*)0x00480004
#define		Uart2IIR						*(volatile unsigned char*)0x00480008
#define		Uart2LCR						*(volatile unsigned char*)0x0048000c
#define		Uart2LSR						*(volatile unsigned char*)0x00480014
#define		Uart2MCR						*(volatile unsigned char*)0x00480010
#define		Uart2MSR						*(volatile unsigned char*)0x00480018
#define		Uart2DLL						*(volatile unsigned char*)0x00480000
#define		Uart2DLM						*(volatile unsigned char*)0x00480004
/*========================================================================*/

/*=======================Define Flash Base Address========================*/
#define		FlashMap0BaseAddr					0x01000000
#define		FlashMap1BaseAddr					0X90000000
/*========================================================================*/

void InitC6202(void)
{
	EMIF_GCTL = 0x00003071;/*Enable SDRAM, disenable SBSRAM*/
	EMIF_CE0 = 0x0ffff3f23;/*UART,DPRAM,EPLD2,Manual*/
	EMIF_CE1 = 0x0ffff3f23;/*FLASH*/
	EMIF_CE2 = 0x0ffff3f33;/*SDRAM*/
	EMIF_CE3 = 0x0ffff3f23;/*ImageBoard FPGA*/
	EMIF_SDRAMCTL = 0x7227000;/*SDRAM Control Register*/
	EMIF_SDRAMREF = 0x4e1;
}