top.vhdl

FPGA读SRAM中的数再传给CY7C68013

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
  port( clk  : 	in std_logic;
  	   reset:		in std_logic;

        slwr: 		buffer std_logic;
	   pktend: 	out std_logic;
	   fifoaddr: 	out std_logic_vector(1 downto 0);
	   fifodata: 	out std_logic_vector(7 downto 0);
        full_flag : in std_logic;	  -- FLAGB pin
	  
	   led:		out std_logic;
	   addr_SRAM:	out std_logic_vector(15 downto 0);
	   data_SRAM:	inout  std_logic_vector(7 downto 0);
	   WE_SRAM:	out std_logic;
    	   OE_SRAM:	out std_logic;
	   CE_SRAM:	out std_logic;
	   LB_SRAM:	out std_logic;
	   UB_SRAM:	out std_logic
	   ) ;       
end top;

architecture Behavioral of top is

signal  count : std_logic_vector(10 downto 0);
signal  inclk: std_logic;

begin

process(clk)
  begin
    	if clk'event and clk='1' then
	  count<=count+'1'; 
	end if;
end process;

inclk<=count(10);

process(inclk, reset)

variable temp_addr_SRAM: std_logic_vector(15 downto 0);	-- 地址变量
variable data_out:		std_logic_vector(7 downto 0);	 	-- 数据变量
variable state:	integer range 0 to 3;		  		-- 状态变量
variable is_end:	std_logic; 					     -- 读数据结束标志
variable flag:   std_logic;

begin

if(inclk'event and inclk='1') then

	if reset='1' then	-- 复位
		fifoaddr<="10";	-- EP6
		pktend<='1';	
		OE_SRAM<='0';	-- 输出使能
		CE_SRAM<='0';	-- 芯片使能
		WE_SRAM<='1';	-- 写禁能
		LB_SRAM<='1';	-- 低位禁能
		UB_SRAM<='1';	-- 高位禁能
		temp_addr_SRAM:=(others=>'0');	-- 地址初始化
		led<='1';		-- LED 暗
		slwr<='1';
		is_end:='0';	-- 写结束标芯初始化
		state:=0;	 	-- 状态变量初始化
	
	else
		if is_end='0' then	 -- 读数据没有结束
			case state is
				when 0 => 
					slwr<='1';    -- deassert SLWR, 地址加1
					data_SRAM<=(others=>'Z');   -- 给数据线上送高阻 
					LB_SRAM<='0'; 	 -- 低位使能
        				addr_SRAM<=temp_addr_SRAM;  -- 送地址
					state:=1;				   -- 转到状态1
				when 1 =>
					data_out:=data_SRAM;	   -- 送数据
					state:=2;
				when 2 =>	
				     flag:=full_flag; 	--and start;
					if flag='1' then	   -- check full flag
						fifodata<=data_out;	   -- not full, drive data to bus
						slwr<='0';      -- assert  SLWR
						state:=3;
			 		else  
						state:=2;
			   		end if;
				when 3 =>
					temp_addr_SRAM:= temp_addr_SRAM+1;	-- 地址变量加1
					state:=0;
					if temp_addr_SRAM="0001000000000000" then -- 已读完
						slwr<='1';
						is_end:='1';	     -- 写结束标志置位
					end if;

					
		  	end case;
		end if;
	end if;
end if;
end process;

end 	 Behavioral;