vhdl－ad0809转换程序.txt

1.AD0809转换器的vhdl实现 2.用状态机来实现不同状态的动态切换

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
   PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        CLK,EOC:IN STD_LOGIC;
         ALE,START,OE,ADDA,LOCK0:OUT STD_LOGIC;
         Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ADCINT;
ARCHITECTURE BEHAV OF ADCINT IS
TYPE STATES IS (ST0,ST1,ST2,ST3,ST4);--定义各状态类型
   SIGNAL CURRENT_STATE,NEXT_STATE:STATES:=ST0;
   SIGNAL REGL  :STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL LOCK  :STD_LOGIC;--转换后数据的输出锁存时钟信号
  BEGIN
    ADDA<='1';    --当ADDA<＝'0',模拟信号进入0809通道0；当ADDA<='1',则进入通道1
    Q<=REGL;
    LOCK0<=LOCK;
   COM:PROCESS(CURRENT_STATE,EOC)  --规定各种状态转换方式
       BEGIN
      CASE  CURRENT_STATE IS
       WHEN ST0=> ALE<='0';START<='0';LOCK<='0';OE<='0';
                   NEXT_STATE<= ST1;   --0809初始化
       WHEN ST1=> ALE<='1';START<='1';LOCK<='0';OE<='0';
                   NEXT_STATE<= ST2;   --启动采样
       WHEN ST2=> ALE<='0';START<='0';LOCK<='0';OE<='0';
         IF (EOC='1') THEN NEXT_STATE<=ST3;  --EOC=1表明转换结束
           ELSE NEXT_STATE <=ST2;            --转换未结束，继续等待
         END IF;
       WHEN ST3=> ALE<='0';START<='0';LOCK<='0';OE<='1';
                   NEXT_STATE<= ST4;    --开启OE，输出转换好的数据
       WHEN ST4=> ALE<='0';START<='0';LOCK<='1';OE<='1';
                   NEXT_STATE<= ST0;
       WHEN OTHERS =>NEXT_STATE <=ST0;
     END CASE;
  END PROCESS COM;
  
  REG:PROCESS(CLK)
      BEGIN
        IF (CLK'EVENT AND CLK='1') THEN CURRENT_STATE <=NEXT_STATE;
         END IF;
      END PROCESS;    --由信号CURRENT_STATE将当前状态值带出此进程：REG
  LATCH1:PROCESS (LOCK)--此进程中，在lock的上升沿，将转换好的数据锁入
          BEGIN
           IF  LOCK='1' AND LOCK'EVENT  THEN  REGL <=D;
           END IF;
         END PROCESS  LATCH1;
  END BEHAV;