📄 config.lst
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C51 COMPILER V7.05 CONFIG 12/20/2006 22:50:31 PAGE 1
C51 COMPILER V7.05, COMPILATION OF MODULE CONFIG
OBJECT MODULE PLACED IN config.OBJ
COMPILER INVOKED BY: D:\SiLabs\MCU\IDEfiles\C51\BIN\C51.exe config.c DB OE
stmt level source
1 //---------------------------------------------------------------
2 // CYGNAL Integrated Products
3 //
4 // C Code Configuration Tool: F020 INITIALIZATION/CONFIGURATION CODE
5 //----------------------------------------------------------------
6 // This file is read only. To insert the code into your
7 // application, simply cut and paste or use the "Save As"
8 // command in the file menu to save the file in your project
9 // directory.
10 //----------------------------------------------------------------
11
12 //----------------------------------------------------------------
13 // INCLUDES
14 //----------------------------------------------------------------
15
16 #include <C8051F020.h> // Register definition file.
17
18 //------------------------------------------------------------------------------------
19 // Global CONSTANTS
20 //------------------------------------------------------------------------------------
21
22 //------------------------------------------------------------------------------------
23 // Function PROTOTYPES
24 //------------------------------------------------------------------------------------
25
26 //------------------------------------------------------------------------------------
27 // Config Routine
28 //------------------------------------------------------------------------------------
29 void config (void) {
30 1
31 1 //Local Variable Definitions
32 1 int n = 0;
33 1
34 1
35 1
36 1
37 1
38 1
39 1 //----------------------------------------------------------------
40 1 // Watchdog Timer Configuration
41 1 //
42 1 // WDTCN.[7:0]: WDT Control
43 1 // Writing 0xA5 enables and reloads the WDT.
44 1 // Writing 0xDE followed within 4 clocks by 0xAD disables the WDT
45 1 // Writing 0xFF locks out disable feature.
46 1 //
47 1 // WDTCN.[2:0]: WDT timer interval bits
48 1 // NOTE! When writing interval bits, bit 7 must be a 0.
49 1 //
50 1 // Bit 2 | Bit 1 | Bit 0
51 1 //------------------------
52 1 // 1 | 1 | 1 Timeout interval = 1048576 x Tsysclk
53 1 // 1 | 1 | 0 Timeout interval = 262144 x Tsysclk
54 1 // 1 | 0 | 1 Timeout interval = 65636 x Tsysclk
55 1 // 1 | 0 | 0 Timeout interval = 16384 x Tsysclk
C51 COMPILER V7.05 CONFIG 12/20/2006 22:50:31 PAGE 2
56 1 // 0 | 1 | 1 Timeout interval = 4096 x Tsysclk
57 1 // 0 | 1 | 0 Timeout interval = 1024 x Tsysclk
58 1 // 0 | 0 | 1 Timeout interval = 256 x Tsysclk
59 1 // 0 | 0 | 0 Timeout interval = 64 x Tsysclk
60 1 //
61 1 //------------------------
62 1
63 1 WDTCN = 0x07; // Watchdog Timer Control Register
64 1
65 1 //----------------------------------------------------------------
66 1 // CROSSBAR REGISTER CONFIGURATION
67 1 //
68 1 // NOTE: The crossbar register should be configured before any
69 1 // of the digital peripherals are enabled. The pinout of the
70 1 // device is dependent on the crossbar configuration so caution
71 1 // must be exercised when modifying the contents of the XBR0,
72 1 // XBR1, and XBR2 registers. For detailed information on
73 1 // Crossbar Decoder Configuration, refer to Application Note
74 1 // AN001, "Configuring the Port I/O Crossbar Decoder".
75 1 //----------------------------------------------------------------
76 1
77 1 // Configure the XBRn Registers
78 1
79 1 XBR0 = 0x00; // XBAR0: Initial Reset Value
80 1 XBR1 = 0x00; // XBAR1: Initial Reset Value
81 1 XBR2 = 0x00; // XBAR2: Initial Reset Value
82 1 // Select Pin I/0
83 1
84 1 // NOTE: Some peripheral I/O pins can function as either inputs or
85 1 // outputs, depending on the configuration of the peripheral. By default,
86 1 // the configuration utility will configure these I/O pins as push-pull
87 1 // outputs.
88 1 // Port configuration (1 = Push Pull Output)
89 1 P0MDOUT = 0x00; // Output configuration for P0
90 1 P1MDOUT = 0x00; // Output configuration for P1
91 1 P2MDOUT = 0x00; // Output configuration for P2
92 1 P3MDOUT = 0x00; // Output configuration for P3
93 1 P74OUT = 0x00; // Output configuration for P4-7
94 1
95 1 P1MDIN = 0xFF; // Input configuration for P1
96 1
97 1 // View port pinout
98 1
99 1 // The current Crossbar configuration results in the
100 1 // following port pinout assignment:
101 1 // Port 0
102 1 // P0.0 = GP I/O (Open-Drain Output/Input)
103 1 // P0.1 = GP I/O (Open-Drain Output/Input)
104 1 // P0.2 = GP I/O (Open-Drain Output/Input)
105 1 // P0.3 = GP I/O (Open-Drain Output/Input)
106 1 // P0.4 = GP I/O (Open-Drain Output/Input)
107 1 // P0.5 = GP I/O (Open-Drain Output/Input)
108 1 // P0.6 = GP I/O (Open-Drain Output/Input)
109 1 // P0.7 = GP I/O (Open-Drain Output/Input)
110 1
111 1 // Port 1
112 1 // P1.0 = GP I/O (Open-Drain Output/Input)(Digital)
113 1 // P1.1 = GP I/O (Open-Drain Output/Input)(Digital)
114 1 // P1.2 = GP I/O (Open-Drain Output/Input)(Digital)
115 1 // P1.3 = GP I/O (Open-Drain Output/Input)(Digital)
116 1 // P1.4 = GP I/O (Open-Drain Output/Input)(Digital)
117 1 // P1.5 = GP I/O (Open-Drain Output/Input)(Digital)
C51 COMPILER V7.05 CONFIG 12/20/2006 22:50:31 PAGE 3
118 1 // P1.6 = GP I/O (Open-Drain Output/Input)(Digital)
119 1 // P1.7 = GP I/O (Open-Drain Output/Input)(Digital)
120 1
121 1 // Port 2
122 1 // P2.0 = GP I/O (Open-Drain Output/Input)
123 1 // P2.1 = GP I/O (Open-Drain Output/Input)
124 1 // P2.2 = GP I/O (Open-Drain Output/Input)
125 1 // P2.3 = GP I/O (Open-Drain Output/Input)
126 1 // P2.4 = GP I/O (Open-Drain Output/Input)
127 1 // P2.5 = GP I/O (Open-Drain Output/Input)
128 1 // P2.6 = GP I/O (Open-Drain Output/Input)
129 1 // P2.7 = GP I/O (Open-Drain Output/Input)
130 1
131 1 // Port 3
132 1 // P3.0 = GP I/O (Open-Drain Output/Input)
133 1 // P3.1 = GP I/O (Open-Drain Output/Input)
134 1 // P3.2 = GP I/O (Open-Drain Output/Input)
135 1 // P3.3 = GP I/O (Open-Drain Output/Input)
136 1 // P3.4 = GP I/O (Open-Drain Output/Input)
137 1 // P3.5 = GP I/O (Open-Drain Output/Input)
138 1 // P3.6 = GP I/O (Open-Drain Output/Input)
139 1 // P3.7 = GP I/O (Open-Drain Output/Input)
140 1
141 1 EMI0CF = 0x00; // External Memory Configuration Register
142 1
143 1 //----------------------------------------------------------------
144 1 // Comparators Register Configuration
145 1 //
146 1 // Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
147 1 //------------------------------------------------------------------
148 1 // R/W | R | R/W | R/W | R/W | R/W | R/W | R/W
149 1 //------------------------------------------------------------------
150 1 // Enable | Output | Rising | Falling| Positive | Negative
151 1 // | State | Edge | Edge | Hysterisis | Hysterisis
152 1 // | Flag | Int. | Int. | 00: Disable | 00: Disable
153 1 // | | Flag | Flag | 01: 5mV | 01: 5mV
154 1 // | | | | 10: 10mV | 10: 10mV
155 1 // | | | | 11: 20mV | 11: 20mV
156 1 // ----------------------------------------------------------------
157 1
158 1 CPT0CN = 0x00; // Comparator 0 Control Register
159 1
160 1
161 1 CPT1CN = 0x00; // Comparator 1 Control Register
162 1
163 1 //Comp1 marker
164 1
165 1 //----------------------------------------------------------------
166 1 // Oscillator Configuration
167 1 //----------------------------------------------------------------
168 1
169 1 OSCXCN = 0x67; // EXTERNAL Oscillator Control Register
170 1 for (n = 0; n < 255; n++) ; // wait for osc to start
171 1 while ( (OSCXCN & 0x80) == 0 ); // wait for xtal to stabilize
172 1
173 1
174 1
175 1
176 1
177 1
178 1
179 1 OSCICN = 0x0C; // Internal Oscillator Control Register
C51 COMPILER V7.05 CONFIG 12/20/2006 22:50:31 PAGE 4
180 1
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