📄 main.lst
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200 1 ADC0LTH = 0x00; // ADC Less-Than High Byte Register
201 1 ADC0LTL = 0x00; // ADC Less-Than Low Byte Register
202 1 ADC0GTH = 0xFF; // ADC Greater-Than High Byte Register
203 1 ADC0GTL = 0xFF; // ADC Greater-Than Low Byte Register
204 1
205 1 AMX1SL = 0x00; // AMUX1 Channel Select Register
206 1 ADC1CF = 0xF8; // ADC1 Configuration Register
207 1 ADC1CN = 0x00; // ADC1 Control Register
208 1
209 1 //----------------------------------------------------------------
210 1 // DAC Configuration
211 1 //----------------------------------------------------------------
212 1
213 1 DAC0CN = 0x00; // DAC0 Control Register
214 1 DAC0L = 0x00; // DAC0 Low Byte Register
215 1 DAC0H = 0x00; // DAC0 High Byte Register
216 1
217 1 DAC1CN = 0x00; // DAC1 Control Register
218 1 DAC1L = 0x00; // DAC1 Low Byte Register
219 1 DAC1H = 0x00; // DAC1 High Byte Register
220 1
221 1 //----------------------------------------------------------------
222 1 // SPI Configuration
223 1 //----------------------------------------------------------------
224 1
225 1 SPI0CN = 0x00; // SPI Control Register
226 1 SPI0CFG = 0x00; // SPI Configuration Register
227 1 SPI0CKR = 0x00; // SPI Clock Rate Register
228 1
229 1 //----------------------------------------------------------------
230 1 // UART Configuration
231 1 //----------------------------------------------------------------
232 1
233 1 SCON0 = 0x40;
234 1 SCON0 &= 0xFC; // Serial Port Control Register
235 1 SADEN0 = 0x00; // Serial 0 Slave Address Enable
236 1 SADDR0 = 0x00; // Serial 0 Slave Address Register
237 1
238 1 PCON = 0x00; // Power Control Register
239 1
240 1 SCON1 = 0x00; // Serial Port 1 Control Register
241 1 SADEN1 = 0x00; // Serial 1 Slave Address Enable
C51 COMPILER V7.05 MAIN 12/22/2006 16:56:03 PAGE 5
242 1 SADDR1 = 0x00; // Serial 1 Slave Address Register
243 1
244 1 //----------------------------------------------------------------
245 1 // SMBus Configuration
246 1 //----------------------------------------------------------------
247 1
248 1 SMB0CN = 0x00; // SMBus Control Register
249 1 SMB0ADR = 0x00; // SMBus Address Register
250 1 SMB0CR = 0x00; // SMBus Clock Rate Register
251 1
252 1
253 1 //----------------------------------------------------------------
254 1 // PCA Configuration
255 1 //----------------------------------------------------------------
256 1
257 1 PCA0MD = 0x00; // PCA Mode Register
258 1 PCA0CN = 0x00; // PCA Control Register
259 1 PCA0H = 0x00; // PCA Counter/Timer High Byte
260 1 PCA0L = 0x00; // PCA Counter/Timer Low Byte
261 1
262 1
263 1 //Module 0
264 1 PCA0CPM0 = 0x00; // PCA Capture/Compare Register 0
265 1 PCA0CPL0 = 0x00; // PCA Counter/Timer Low Byte
266 1 PCA0CPH0 = 0x00; // PCA Counter/Timer High Byte
267 1
268 1 //Module 1
269 1 PCA0CPM1 = 0x00; // PCA Capture/Compare Register 1
270 1 PCA0CPL1 = 0x00; // PCA Counter/Timer Low Byte
271 1 PCA0CPH1 = 0x00; // PCA Counter/Timer High Byte
272 1
273 1 //Module 2
274 1 PCA0CPM2 = 0x00; // PCA Capture/Compare Register 2
275 1 PCA0CPL2 = 0x00; // PCA Counter/Timer Low Byte
276 1 PCA0CPH2 = 0x00; // PCA Counter/Timer High Byte
277 1
278 1 //Module 3
279 1 PCA0CPM3 = 0x00; // PCA Capture/Compare Register 3
280 1 PCA0CPL3 = 0x00; // PCA Counter/Timer Low Byte
281 1 PCA0CPH3 = 0x00; // PCA Counter/Timer High Byte
282 1
283 1 //Module 4
284 1 PCA0CPM4 = 0x00; // PCA Capture/Compare Register 4
285 1 PCA0CPL4 = 0x00; // PCA Counter/Timer Low Byte
286 1 PCA0CPH4 = 0x00; // PCA Counter/Timer High Byte
287 1
288 1 //----------------------------------------------------------------
289 1 // Timer Configuration
290 1 //----------------------------------------------------------------
291 1
292 1 CKCON = 0x00; // Clock Control Register
293 1 TH0 = 0x00; // Timer 0 High Byte
294 1 TL0 = 0x00; // Timer 0 Low Byte
295 1 TH1 = 0x00; // Timer 1 High Byte
296 1 TL1 = 0x00; // Timer 1 Low Byte
297 1 TMOD = 0x20; // Timer Mode Register
298 1 TCON = 0x40; // Timer Control Register
299 1
300 1 RCAP2H = 0xFF; // Timer 2 Capture Register High Byte
301 1 RCAP2L = 0xDC; // Timer 2 Capture Register Low Byte
302 1 TH2 = 0xFF; // Timer 2 High Byte
303 1 TL2 = 0xEC; // Timer 2 Low Byte
C51 COMPILER V7.05 MAIN 12/22/2006 16:56:03 PAGE 6
304 1 T2CON = 0x34; // Timer 2 Control Register
305 1
306 1 TMR3RLL = 0x00; // Timer 3 Reload Register Low Byte
307 1 TMR3RLH = 0x00; // Timer 3 Reload Register High Byte
308 1 TMR3H = 0x00; // Timer 3 High Byte
309 1 TMR3L = 0x00; // Timer 3 Low Byte
310 1 TMR3CN = 0x00; // Timer 3 Control Register
311 1
312 1 RCAP4H = 0x00; // Timer 4 Capture Register High Byte
313 1 RCAP4L = 0x00; // Timer 4 Capture Register Low Byte
314 1 TH4 = 0x00; // Timer 4 High Byte
315 1 TL4 = 0x00; // Timer 4 Low Byte
316 1 T4CON = 0x00; // Timer 4 Control Register
317 1
318 1 //----------------------------------------------------------------
319 1 // Reset Source Configuration
320 1 //
321 1 // Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
322 1 //------------------------------------------------------------------
323 1 // R | R/W | R/W | R/W | R | R | R/W | R
324 1 //------------------------------------------------------------------
325 1 // JTAG |Convert | Comp.0 | S/W | WDT | Miss. | POR | HW
326 1 // Reset |Start | Reset/ | Reset | Reset | Clock | Force | Pin
327 1 // Flag |Reset/ | Enable | Force | Flag | Detect| & | Reset
328 1 // |Enable | Flag | & | | Flag | Flag | Flag
329 1 // |Flag | | Flag | | | |
330 1 //------------------------------------------------------------------
331 1 // NOTE! : Comparator 0 must be enabled before it is enabled as a
332 1 // reset source.
333 1 //
334 1 // NOTE! : External CNVSTR must be enalbed through the crossbar, and
335 1 // the crossbar enabled prior to enabling CNVSTR as a reset source
336 1 //------------------------------------------------------------------
337 1
338 1 RSTSRC = 0x00; // Reset Source Register
339 1
340 1
341 1 //----------------------------------------------------------------
342 1 // Interrupt Configuration
343 1 //----------------------------------------------------------------
344 1
345 1 IE = 0x00; //Interrupt Enable
346 1 IP = 0x00; //Interrupt Priority
347 1 EIE1 = 0x00; //Extended Interrupt Enable 1
348 1 EIE2 = 0x00; //Extended Interrupt Enable 2
349 1 EIP1 = 0x00; //Extended Interrupt Priority 1
350 1 EIP2 = 0x00; //Extended Interrupt Priority 2
351 1
352 1
353 1
354 1 // other initialization code here...
355 1
356 1 WDTCN=0xDE;
357 1
358 1 WDTCN=0xAD;
359 1
360 1 } //End of config
361
362 //#include <C8051F020.h>
363 void trbyte(char a)
364 {
365 1 IE=0;
C51 COMPILER V7.05 MAIN 12/22/2006 16:56:03 PAGE 7
366 1 SBUF0=a;
367 1
368 1 while (!TI0)
369 1 { };
370 1 TI0=0;
371 1
372 1 }
373
374 void trstring(char *a)
375 {
376 1 for( ;*a!='\0';a++)
377 1 trbyte(*a);
378 1
379 1 }
380
381
382 void main( )
383 {
384 1
385 1
386 1 char a[]="hello world this is write by yang\n";
387 1 config();
388 1 trstring(a);
389 1 while (1){
390 2 }
391 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 299 ----
CONSTANT SIZE = 35 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 35
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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