main.lst

新华龙 C8051F020开发板串口程序 只有串口输入

C51 COMPILER V7.05   MAIN                                                                  12/22/2006 16:56:03 PAGE 1   


C51 COMPILER V7.05, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: D:\SiLabs\MCU\IDEfiles\C51\BIN\C51.exe main.c DB OE

stmt level    source

   1          #include <C8051F020.h>
   2          #include <config.h>
   3          #include <trasmit.h>
   4          //---------------------------------------------------------------
   5          // CYGNAL Integrated Products 
   6          //
   7          // C Code Configuration Tool: F020 INITIALIZATION/CONFIGURATION CODE
   8          //----------------------------------------------------------------
   9          // This file is read only. To insert the code into your  
  10          // application, simply cut and paste or use the "Save As" 
  11          // command in the file menu to save the file in your project 
  12          // directory. 
  13          //----------------------------------------------------------------
  14          
  15          //----------------------------------------------------------------
  16          // INCLUDES
  17          //----------------------------------------------------------------
  18          
  19          //#include <C8051F020.h>        // Register definition file.
  20          
  21          //------------------------------------------------------------------------------------
  22          // Global CONSTANTS
  23          //------------------------------------------------------------------------------------
  24          
  25          //------------------------------------------------------------------------------------
  26          // Function PROTOTYPES
  27          //------------------------------------------------------------------------------------
  28          
  29          //------------------------------------------------------------------------------------
  30          // Config Routine
  31          //------------------------------------------------------------------------------------
  32          void config (void) {
  33   1      
  34   1      //Local Variable Definitions
  35   1          int n = 0;
  36   1      
  37   1      
  38   1      
  39   1      
  40   1              
  41   1      
  42   1      //----------------------------------------------------------------
  43   1      // Watchdog Timer Configuration
  44   1      //
  45   1      // WDTCN.[7:0]: WDT Control
  46   1      //   Writing 0xA5 enables and reloads the WDT.
  47   1      //   Writing 0xDE followed within 4 clocks by 0xAD disables the WDT
  48   1      //   Writing 0xFF locks out disable feature.
  49   1      //
  50   1      // WDTCN.[2:0]: WDT timer interval bits
  51   1      //   NOTE! When writing interval bits, bit 7 must be a 0.
  52   1      //
  53   1      //  Bit 2 | Bit 1 | Bit 0
  54   1      //------------------------     
  55   1      //    1   |   1   |   1      Timeout interval = 1048576 x Tsysclk
C51 COMPILER V7.05   MAIN                                                                  12/22/2006 16:56:03 PAGE 2   

  56   1      //    1   |   1   |   0      Timeout interval =  262144 x Tsysclk
  57   1      //    1   |   0   |   1      Timeout interval =   65636 x Tsysclk
  58   1      //    1   |   0   |   0      Timeout interval =   16384 x Tsysclk
  59   1      //    0   |   1   |   1      Timeout interval =    4096 x Tsysclk
  60   1      //    0   |   1   |   0      Timeout interval =    1024 x Tsysclk
  61   1      //    0   |   0   |   1      Timeout interval =     256 x Tsysclk
  62   1      //    0   |   0   |   0      Timeout interval =          64 x Tsysclk
  63   1      // 
  64   1      //------------------------
  65   1      
  66   1              WDTCN = 0x07;   // Watchdog Timer Control Register
  67   1      
  68   1      //----------------------------------------------------------------
  69   1      // CROSSBAR REGISTER CONFIGURATION
  70   1      //
  71   1      // NOTE: The crossbar register should be configured before any  
  72   1      // of the digital peripherals are enabled. The pinout of the 
  73   1      // device is dependent on the crossbar configuration so caution 
  74   1      // must be exercised when modifying the contents of the XBR0, 
  75   1      // XBR1, and XBR2 registers. For detailed information on 
  76   1      // Crossbar Decoder Configuration, refer to Application Note 
  77   1      // AN001, "Configuring the Port I/O Crossbar Decoder". 
  78   1      //----------------------------------------------------------------
  79   1      
  80   1      // Configure the XBRn Registers
  81   1      
  82   1              XBR0 = 0x04;    // XBAR0: Initial Reset Value
  83   1              XBR1 = 0x00;    // XBAR1: Initial Reset Value
  84   1              XBR2 = 0x40;    // XBAR2: Initial Reset Value
  85   1      // Select Pin I/0
  86   1      
  87   1      // NOTE: Some peripheral I/O pins can function as either inputs or 
  88   1      // outputs, depending on the configuration of the peripheral. By default,
  89   1      // the configuration utility will configure these I/O pins as push-pull 
  90   1      // outputs.
  91   1                            // Port configuration (1 = Push Pull Output)
  92   1          P0MDOUT = 0x00; // Output configuration for P0 
  93   1          P1MDOUT = 0x00; // Output configuration for P1 
  94   1          P2MDOUT = 0x00; // Output configuration for P2 
  95   1          P3MDOUT = 0x00; // Output configuration for P3 
  96   1          P74OUT = 0x00;  // Output configuration for P4-7
  97   1      
  98   1          P1MDIN = 0xFF;  // Input configuration for P1
  99   1      
 100   1      // View port pinout
 101   1      
 102   1                      // The current Crossbar configuration results in the 
 103   1                      // following port pinout assignment:
 104   1                      // Port 0
 105   1                      // P0.0 = GP I/O          (Open-Drain Output/Input)
 106   1                      // P0.1 = GP I/O          (Open-Drain Output/Input)
 107   1                      // P0.2 = GP I/O          (Open-Drain Output/Input)
 108   1                      // P0.3 = GP I/O          (Open-Drain Output/Input)
 109   1                      // P0.4 = GP I/O          (Open-Drain Output/Input)
 110   1                      // P0.5 = GP I/O          (Open-Drain Output/Input)
 111   1                      // P0.6 = GP I/O          (Open-Drain Output/Input)
 112   1                      // P0.7 = GP I/O          (Open-Drain Output/Input)
 113   1      
 114   1                      // Port 1
 115   1                      // P1.0 = GP I/O          (Open-Drain Output/Input)(Digital)
 116   1                      // P1.1 = GP I/O          (Open-Drain Output/Input)(Digital)
 117   1                      // P1.2 = GP I/O          (Open-Drain Output/Input)(Digital)
C51 COMPILER V7.05   MAIN                                                                  12/22/2006 16:56:03 PAGE 3   

 118   1                      // P1.3 = GP I/O          (Open-Drain Output/Input)(Digital)
 119   1                      // P1.4 = GP I/O          (Open-Drain Output/Input)(Digital)
 120   1                      // P1.5 = GP I/O          (Open-Drain Output/Input)(Digital)
 121   1                      // P1.6 = GP I/O          (Open-Drain Output/Input)(Digital)
 122   1                      // P1.7 = GP I/O          (Open-Drain Output/Input)(Digital)
 123   1                                              
 124   1                      // Port 2               
 125   1                      // P2.0 = GP I/O          (Open-Drain Output/Input)
 126   1                      // P2.1 = GP I/O          (Open-Drain Output/Input)
 127   1                      // P2.2 = GP I/O          (Open-Drain Output/Input)
 128   1                      // P2.3 = GP I/O          (Open-Drain Output/Input)
 129   1                      // P2.4 = GP I/O          (Open-Drain Output/Input)
 130   1                      // P2.5 = GP I/O          (Open-Drain Output/Input)
 131   1                      // P2.6 = GP I/O          (Open-Drain Output/Input)
 132   1                      // P2.7 = GP I/O          (Open-Drain Output/Input)
 133   1      
 134   1                      // Port 3               
 135   1                      // P3.0 = GP I/O          (Open-Drain Output/Input)
 136   1                      // P3.1 = GP I/O          (Open-Drain Output/Input)
 137   1                      // P3.2 = GP I/O          (Open-Drain Output/Input)
 138   1                      // P3.3 = GP I/O          (Open-Drain Output/Input)
 139   1                      // P3.4 = GP I/O          (Open-Drain Output/Input)
 140   1                      // P3.5 = GP I/O          (Open-Drain Output/Input)
 141   1                      // P3.6 = GP I/O          (Open-Drain Output/Input)
 142   1                      // P3.7 = GP I/O          (Open-Drain Output/Input)
 143   1      
 144   1          EMI0CF = 0x00;    // External Memory Configuration Register
 145   1      
 146   1      //----------------------------------------------------------------
 147   1      // Comparators Register Configuration
 148   1      //
 149   1      // Bit 7  | Bit 6  | Bit 5  | Bit 4  | Bit 3 | Bit 2 | Bit 1 | Bit 0
 150   1      //------------------------------------------------------------------     
 151   1      //  R/W   |    R   |  R/W   |  R/W   |  R/W  |  R/W  |  R/W  |  R/W
 152   1      //------------------------------------------------------------------
 153   1      // Enable | Output | Rising | Falling|  Positive     |  Negative    
 154   1      //        | State  | Edge   | Edge   |  Hysterisis   |  Hysterisis    
 155   1      //        | Flag   | Int.   | Int.   |  00: Disable  |  00: Disable
 156   1      //        |        | Flag   | Flag   |  01:  5mV     |  01:  5mV  
 157   1      //        |        |        |        |  10: 10mV     |  10: 10mV
 158   1      //        |        |        |        |  11: 20mV     |  11: 20mV 
 159   1      // ----------------------------------------------------------------
 160   1      
 161   1              CPT0CN = 0x00;  // Comparator 0 Control Register
 162   1              
 163   1      
 164   1              CPT1CN = 0x00;  // Comparator 1 Control Register
 165   1              
 166   1              //Comp1 marker
 167   1                                              
 168   1      //----------------------------------------------------------------
 169   1      // Oscillator Configuration
 170   1      //----------------------------------------------------------------
 171   1      
 172   1              OSCXCN = 0x67;  // EXTERNAL Oscillator Control Register 
 173   1          for (n = 0; n < 255; n++) ;            // wait for osc to start
 174   1          while ( (OSCXCN & 0x80) == 0 );        // wait for xtal to stabilize
 175   1      
 176   1      
 177   1      
 178   1      
 179   1      
C51 COMPILER V7.05   MAIN                                                                  12/22/2006 16:56:03 PAGE 4   

 180   1      
 181   1      
 182   1              OSCICN = 0x0C;  // Internal Oscillator Control Register
 183   1      
 184   1              
 185   1      //----------------------------------------------------------------
 186   1      // Reference Control Register Configuration
 187   1      //----------------------------------------------------------------
 188   1      
 189   1              REF0CN = 0x00;  // Reference Control Register
 190   1      
 191   1      //----------------------------------------------------------------
 192   1      // ADC Configuration
 193   1      //----------------------------------------------------------------
 194   1      
 195   1              AMX0CF = 0x60;  // AMUX Configuration Register
 196   1              AMX0SL = 0x00;  // AMUX Channel Select Register
 197   1              ADC0CF = 0xF8;  // ADC Configuration Register
 198   1              ADC0CN = 0x00;  // ADC Control Register
 199   1