fw.src

Wince4.2 BSP for SH4 engineering development board

	bf Check_72_85
	mov.l	#BSC_MCR_MEM_TYPE_SDRAM_60_72, r2
	ldc		r2,r2_bank
	mov.l	#BSC_SDMR_PALL_MRSET_60_72, r2
	ldc		r2,r3_bank
	bra		BSC_MCR_Exit
	nop
Check_72_85:
	mov.l	#85000000,r1
	cmp/hs	r3,r1
	bf Check_85_100
	mov.l	#BSC_MCR_MEM_TYPE_SDRAM_72_85, r2
	ldc		r2,r2_bank
	mov.l	#BSC_SDMR_PALL_MRSET_72_85, r2
	ldc		r2,r3_bank
	bra		BSC_MCR_Exit
	nop
Check_85_100:
	mov.l	#BSC_MCR_MEM_TYPE_SDRAM_85_100, r2
	ldc		r2,r2_bank
	mov.l	#BSC_SDMR_PALL_MRSET_85_100, r2
	ldc		r2,r3_bank
BSC_MCR_Exit:


;Enter Self Reflesh mode
	mov.l	#BSC_MCR,r0										; (r0) = ptr memory control register
	mov.l	@R0,r1											; (r1) = memory control register
	mov.l	#(BSC_MCR_RFSH + BSC_MCR_RMODE), r2				; (r2) = RFSH(n/1) and RMODE(n/0) bit on
	or		r2, r1											; memory control register RFSH and RMODE bit set
	mov.l	r1, @r0											; set memory control register

;Set WDT control
	mov.l	#CPG_WTCSR,r0									; (r0) = ptr control / state register
	mov.w	@r0,r1											; (r1) = control / state register
	mov.w  #(CPG_WTCSR_COOKIE + CPG_WTCSR_CKS_4096),r1		; (r1) = WTCSR_COOKIE(h'a500) + CK2(n/2) ,CK1(n/1), CK0(n/0) bit on
	mov.w	r1,@r0											; set control / state register
	
;Set WDT count
	mov.l	#CPG_WTCNT,r0									; (r0) = ptr timer count register
	mov.w	@r0,r1											; (r1) = timer count register
	mov.w	#(CPG_WTCNT_COOKIE + h'00ff),r1					; (r1) = WTCNT_COOKIE(h'5a00) + full count(h'00ff)
	mov.w	r1,@r0											; set timer count register
	
;Set up int handler for wakeup
	mov.l   #Resume, r0										; (r0) = ptr Resume
	mov.l	#h'600, r1
	sub		r1, r0
	ldc		r0, vbr

;Enter Standby mode
	sleep

		.align 4
Resume:														; resume cpu
	
;Restore  MCR
	stc		r2_bank, r0	; BSC_MCR_MEM_TYPE_SDRAM
	mov		#BSC_MCR,r2	; Set memory control,
	mov.l	r0, @r2

	mov.l	#h'FF940190, r1
	mov.b	r1, @r1

MCR_timer:
	mov.l	#h'0000fff0, r0

MCR_loop:
	add		#(-1), r0
	tst		r0, r0
	bf		MCR_loop

    mov.l   #BSC_MCR, r1
    stc     r2_bank, r0 ; BSC_MCR_MEM_TYPE_SDRAM
    mov.l   #BSC_MCR_MRSET, r3
    or      r3, r0
    mov.l   r0, @r1

	stc		r3_bank, r1 ; BSC_SDMR_PALL_MRSET
	mov.b	r1, @r1

;Restore CPG(CPUclock=200MHz)
	mov.l   #CPG_FRQCR, r0									; (r0) = ptr frequency control register	
	mov.l	@r15+,r1										; restor frequency control register
	mov.w	r1, @r0											; set frequency control register

;Wait 10ms for HD64404 clock steady
	mov.l	#h'00200000,r1	
Wait_Loop:
	dt	r1
	bf	Wait_Loop
	nop

;Restore STBCR		
	mov.l	#CPG_STBCR, r0									; (r0) = ptr standby control register
	mov.l	@r15+,r1										; restor standby control register
	mov.b	r1,@r0											; set standby control register	

;Restore TSTR 
	mov.l	#TMU_TSTR,r0									; (r0) = ptr timer start register
	mov.l	@r15+,r1										; restor timer start register
	mov.b	r1,@r0											; set timer start register
	
;Initialize debug serial/ethernet port
    mov     r4, @-r15
    mov     r5, @-r15
    mov     r6, @-r15
    mov     r7, @-r15
	mov.l	#_OEMInitDebugSerial, r0						; (r0) = ptr debugSerial/ethernet port
	jsr		@r0												; initialize debugSerial/ethernet port 
	nop
	
;Restore registers
    mov     @r15+, r7
    mov     @r15+, r6
    mov     @r15+, r5
    mov     @r15+, r4

;Restore FPGA interrupt 
	mov.l	#PF_INTMR,r0									; (r0) = interrupt register
	mov.l	@r15+,r1										; restor interrupt register
	mov.w	r1,@r0											; set interrupt register

;Restore HD64404 interrupt
	mov.l	#INTPRI_MASK,r0									; (r0) = interrupt register
	mov.l	@r15+,r1										; restor interrupt register
	mov.l	r1,@r0											; set interrupt register

;Restore registers
	ldc.l	@r15+, VBR
	lds.l	@r15+, PR
	ldc.l	@r15+, SR

OemPwrOffExit:


	rts
	nop
	.endf

;*****************************************************************************
;*	Function :		_SCIF_ISR
;*	Description :	Interrupt Service Routine for the SCIF
;*	Inputs :		r0 = interrupt disposition info 
;*	Outputs :		r0 = return Interrupt ID.
;*	Notes :			This routine decodes the CPU interrupt status 
;*					register on the CP09 and returns SYSINT_SERIAL
;*					
;*
;*					Registers: r0-r3,r6 available for use.
;*
;*					Entry   in register bank 1, exceptions blocked
;*					Exit    (r0) = interrupt dispostion information
;*                      (see nkintr.h for values)
;*					Uses    r0-r3,r6
;******************************************************************************
	LEAF_ENTRY _SCIF_ISR

	; if we are here, we know that an SCI Interrupt occurred, so I just need
	; to mask it out by accessing the proper priority register and giving
	; it the priority 0.

	mov	#INTC_IPRC, r2				; move the register into r2
	mov	#INTC_IPRC_SCIF_MASK,r1		; move in the mask value
	mov.w	@r2, r3					; get the contents of the IPRC 
	and	r3, r1
	mov.w	r1, @r2					; place in the masked value

	rts
	mov	#SYSINTR_SCIF, r0
	 
	.endf

;*****************************************************************************
;	CPUEnterIdle
; NOTE: Exceptions are blocked when this routine called and must not 
; be reenabled unless the functions is going to return immediately. 
; The SH3 ignores the block bit in the PSR when sleeping so it is 
; not necessary to enable interrupts before issuing the sleep 
; instruction.
;*****************************************************************************
	LEAF_ENTRY _CPUEnterIdle
	sleep
	rts
	nop
	.endf

;*****************************************************************************
;* OEMIdle - system idle
;*
;* This routine is called by the kernel when there are no threads ready to
;* run. The CPU should be put into a reduced power mode and halted. It is important
;* to be able to resume execution quickly upon receiving an interrupt.
;*
;* NOTE: Exceptions are blocked when this routine called and must not be reenabled
;* unless the functions is going to return immediately. The SH4 ignores the block bit
;* in the PSR when sleeping so it is not necessary to enable interrupts before issuing
;* the sleep instruction.
;*
;*	Entry	Exceptions blocked
;*	Exit	none
;*	Uses	r0-r3
;*****************************************************************************
;	LEAF_ENTRY OEMIdle

;	sleep
;	rts
;	nop
;	.endf

;*****************************************************************************
;* OEMNMI - non-maskable interrupt handler
;*
;* This routine is called when a non-maskable interrupt occurs. It should return
;* an interrupt cause the same as other interrupt service routines.
;*
;* Registers: r0-r3,r6 available for use.
;*
;*     Entry   in register bank 1, exceptions blocked
;*     Exit    (r0) = interrupt dispostion information
;*                   (see nkintr.h for values)
;*     Uses    r0
;*****************************************************************************
	LEAF_ENTRY OEMNMI

	mov		#_fInterruptWakeup,r2		; fInterruptWakeup[r0]
	mov		#SYSINTR_NOP, r0			
	add		r0,r2
	mov		#1, r1
	mov.b	r1,@r2
	rts
	nop
	.endf


;*****************************************************************************
;*	Function :		_GetSR
;*	Description :	Get SR
;*	Inputs :		none
;*	Outputs :		SR value
;******************************************************************************

	LEAF_ENTRY _GetSR

    stc     SR, r0
	rts
	nop
	.endf

;*****************************************************************************
;*	Function :		_SetSR
;*	Description :	Set SR
;*	Inputs :		SR value
;*	Outputs :		none
;******************************************************************************

	LEAF_ENTRY _SetSR

    ldc     r4, SR
	rts
	nop
	.endf


	.end