fw.src

Wince4.2 BSP for SH4 engineering development board

;
;    Copyright(c) Renesas Technology Corp. 2002-2003 All rights reserved.
;
;    OEM Adaptation Layer
;
;    File		: fw.src
;	 Created	:
;    Modified   : 2003.08.06
;    Author     : Renesas Technology Corp.
;    Hardware   : RENESAS HS7751RSTC01H (S1-E, ITS-DS5)
;    Target OS  : Microsoft(R) Windows(R) CE .NET 4.2
;	 Notes  	: 
;    History	:
;				  2002. 1.31  
;				  - Modified for HS7751RSTC01H (S1-E, ITS-DS5)
;       		  2002. 5. 2  
;       		  - OEMPowerOff is temporary modified not to be assembled.
;       		  2002. 6. 4  
;       	      - SH7751R and HD64404 bus initialization is modified to refer
;                  include file "CONFIG_BUS.INC".
;                 2002.9.26
;				  - Added _SCIF_ISR. 
;                 - Released

;++
; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
; PARTICULAR PURPOSE.
; Copyright (c) 1995-2000 Microsoft Corporation.  All rights reserved.
;--

    .list OFF
    .include "kxshx.h"
    .include "boot.inc"
    .include "s1e.inc"
    .include "shx.inc"
    .include "oalintr.inc"
    .include "hd64404.inc"
    .include "drv_glob.inc"
    .list ON

    .section .text,code

    .align  4

    .export _OEMExtraCCR
    .export _SH4CacheLines
;_OEMExtraCCR:   .data.l h'000
;_SH4CacheLines: .data.l 512
_OEMExtraCCR:   .data.l h'80000105
_SH4CacheLines: .data.l 1024

    .import KernelStart
    .import _AlarmYear
    .import _OEMInitDebugSerial
	.import	_fInterruptWakeup

    .aif    WITHOUT_BOOTLOADER eq 1
    .include "clock_freq.inc" ; Clock frequency detection, function itself.
    .include "config_bus.inc" ; Bus initialization, function itself.
    .aendi

;/*****************************************************************************
;*      FUNCTION :              StartUp()
;*      DESCRIPTION :   The initial starting point of the system
;*      INPUTS :                None - we are branched to from the reset vector
;*      OUTPUTS :               None, we branch to the main()
;******************************************************************************

    LEAF_ENTRY _StartUp


    mova    strt10, r0
    mov.l   #h'20000000, r2             ; moves from section P1(cached) to P2 (uncached)
    or      r2, r0
    jmp     @r0                         ; jumps to strt10 in section P2
    nop

    .align  4

strt10:	


    mov.l   #TM_SR, r0                  ; release mask etc
    ldc     r0, sr

    mov.l   #h'00000000, r0
    ldc     r0, vbr

    ; When the FRQCR is modified, it creates unstability in the PLL.  For this
    ; reason, when FRQCR is modified, the CPU shuts off.  The Watchdog timer
    ; is used to wake-up of the system, so it must be configured properly before
    ; setting FRQCR. At least 200us is needed for PLL stabilization.

    mov.l   #CPG_WTCSR, r1
    mov.w   #SET_CKS, r0
    mov.w   r0, @r1                     ; Set type of clock count to use in WTCSR
    mov.l   #CPG_WTCNT, r1
    mov.w   #COUNT_INIT, r0
    mov.w   r0, @r1                     ; Set initial value for counter in WTCNT


    ; Set FRQCR if needed. This is left keeping initial value in default to
    ; enable same OS kernel to operate in different CPU clock modes specified
    ; by switch S1-1, S1-2 and S1-3 on the HS7751RSTC01H base board.
;    mov.l   #CPG_FRQCR, r1
;    mov.l   #CPG_FRQCR_CLOCK, r0
;    mov.w   r0, @r1


    .aif     WITHOUT_BOOTLOADER eq 1
    ; When we are starting directly from reset vector, we have to initialize
    ; hardwares related to system bus timing and clocks. This initialization
    ; is described in include file, and refered by both OS kernel and ethernet
    ; bootloader.

    bsr     _ConfigureBusTimings
    nop

    .aendi

    ; Disable the Cache, the kernel will take care of it.

    mov.l   #CCN_CCR, r1                ; ptr to Cache control register
    mov.l   #CCN_CCR_DISABLE, r0
    mov.l   r0, @r1                     ; disable the cache

    mov.l   #h'0000fff0, r0
CACHE_LOOP
    add     #(-1), r0
    tst     r0, r0
    bf      CACHE_LOOP

    ; Load the Kernel and JUMP

    mov.l   #KernelStart, r0            ; load address of KernelStart
    mov.l   #h'20000000, r2             ; moves from section P1(cached) to P2 (uncached)
    or      r2, r0

    jmp     @r0                         ; execute KernelStart in P1 section
    nop

    .endf

;************************************************************************************
; SH4 RTC Alarm interrupt service routine
;
;	This routine is invoked when the real time matches the alarm time. Since the year
; is not included as part of the alarm time, the year must be checked and the interrupt
; will be ignored if the year doesn't match.
;
; Registers: r0-r3, r6 available for use
;
;      Entry   in register bank 1, exceptions blocked
;      Exit    (r0) = interrupt dispostion information
;                      (see nkintr.h for values)
;      Uses    r0-r3,r6
; Clear the alarm flag.

	LEAF_ENTRY _AlarmISR
	mov		#RTC_RCR1, r2					; (r0) = RTC control register 1 contents
	mov.b	@r2, r0
	mov		#~RTC_RCR1_AF, r1
	and		r1, r0
	mov.b	r0, @r2							; clear alarm flag in control register 1

; Compare the current year with the alarm year.

	mov		#_AlarmYear, r1					; (r1) = ptr to alarm year
	mov.w	@r1, r1							; (r1) = alarm year value
	mov		#RTC_RYRCNT, r3					; (r3) = ptr to RYRCNT (current year)
	mov.w	@r3, r2							; (r2) = current year (in BCD)
	cmp/eq	r1, r2
	bf/s	aisr40							; year matches, signal the alarm
	mov		#SYSINTR_NOP, r0

	mov		#RTC_RCR1, r2					; (r0) = RTC control register 1 contents
	mov.b	@r2, r0
	mov		#~(RTC_RCR1_AIE|RTC_RCR1_AF) , r1
	and		r1 , r0
	mov.b	r0, @r2							; Disable alarm interrupt in control register 1
	mov		#SYSINTR_RTC_ALARM, r0			; (r0) = interrupt cause

aisr40:
	rts
	nop
	.endf

;*****************************************************************************
;* OEMPowerOff - OFF button handler
;*
;* This routine is invoked when the OFF button is pressed. It is responsible
;* for any final power off state and putting the cpu into standby.
;*
;*	Entry	none
;*	Exit	none
;*	Uses	r0-r3
;*****************************************************************************
	LEAF_ENTRY _OEMPowerOffsh

	; Don't power down if image is loaded into RAM
	mov     #h'0C000000, r0
	sts     PR, r1
	and     r1,r0
	tst     r0,r0
	bt      OemPwrOffContinue
	rts
	nop
OemPwrOffContinue:

;Save registers on stack
	stc.l	SR, @-r15
	sts.l	PR, @-r15
	stc.l	VBR, @-r15

;Unmask interrupts above pri 1 for resume,set block bit,use reg bank1
	mov.l	#h'70000010, r0
	ldc		r0, SR                                                                                                                                                    

;HD64404 interrupt all mask
	mov.l	#INTPRI_MASK,r0									; (r0) = ptr interrupt register
	mov.l	@r0,r1											; (r1) = interrupt register  
	mov.l	r1,@-r15										; store interrupt register
	mov.l	#h'ffffffff,r2									; (r2) = all bit mask(n/31-n/0)
	or		r2,r1											; interrupt register all bit mask
	mov.l	r1,@r0											; set interrupt register

;Power-off HD64404


;FPGA interrupt mask
	mov.l	#PF_INTMR,r0									; (r0) = ptr interrupt register
	mov.w	@r0,r1											; (r1) = interrupt register
	mov.l	r1,@-r15										; store interrupt register
	mov.w	#(PF_INTMR_MASK_PCI + PF_INTMR_MASK_ETHER + PF_INTMR_MASK_PCMCIA),r2 ; (r2) = bit on 
	or		r2,r1											; interrupt register bit mask
	mov.w	r1,@r0											; set interrupt register

;Save TSTR on stack
	mov.l	#TMU_TSTR,r0									; (r0) = ptr timer start register
	mov.b	@r0,r1											; (r1) = timer start register
	mov.l	r1,@-r15										; store timer start register

;Set STBCR
	mov.l   #CPG_STBCR, r0									; (r0) = ptr standby control register
	mov.b	@r0,r1											; (r1) = standby control register
    mov.l	r1,@-r15										; store standby control register	
	mov		#CPG_STBCR_STBY,r2								; (r2) = STBY bit(n/7) on
    or		r2,r1											; standby control register STBY bit on
    mov.b	r1, @r0											; set standby control register

;Set CPG 
	mov.l   #CPG_FRQCR, r0									; (r0) = ptr frequency control register
	mov.w	@r0,r1											; (r1) = frequency control registe
	mov.l	r1,@-r15										; store frequency control register
;	mov.w	#CPG_FRQCR_CLOCK2, r1							; (r1) = CPUclock
;	mov.w	r1, @r0											; set frequency control register

;Save BSC_MCR to r2_bank, r3_bank
	mov.l	#CLOCK_SYSTEM_BUS_FREQUENCY,r0
	mov.l	@r0,r3
Check_60_72:
	mov.l	#72000000,r1
	cmp/hs	r3,r1