init.src

Wince4.2 BSP for SH4 engineering development board

;
;       Copyright (c) Renesas Technology Corp. 1999-2003 All Rights Reserved.
; 
;       Ethernet Bootloader
;
; ----------------------------------------------------------------------------
; 
;   FILE      : INIT.SRC
;   CREATED   : 1999.04.26 (for PFM-DS6)
;   MODIFIED  : 2003.08.06
;   AUTHOR    : Renesas Technology Corp.
;   HARDWARE  : RENESAS HS7751RSTC01H (S1-E, ITS-DS5)
;   TARGET OS : Microsoft(R) Windows(R) CE .NET 4.2
;   NOTES     : 
;   FUNCTION  : System initialization and code launcher used in EBOOT
;   HISTORY   :
;               1999. 4.26
;               - Released for PFM-DS6.
;               2001. 7. 6
;               - Modified for ITS-DS2A (BigSur with HD64404).
;               (Detailed histories for previous platforms are omitted.)
;               2002. 2.20
;               - Modified for HS7751RSTC01H (S1-E, ITS-DS5).
;               2002. 6. 4
;               - SH7751R and HD64404 bus initialization is moved to include
;                file "CONFIG_BUS.INC".
;               2002. 9. 9
;               - Header style is modified.

;
;   Copyright (c) 1995-1998  Microsoft Corporation.
;

    .list OFF
    .include "kxshx.h"
    .include "shx.inc"
    .include "boot.inc"
    .include "s1e.inc"
    .include "hd64404.inc"
    .include "drv_glob.inc"
    .list ON

    .import _main

    ; DetectClockFreq() for clock frequency detection.
    .include "clock_freq.inc" ; Actually this is function body.

    ; ConfigureBusTimings() for bus configuration.
    .include "config_bus.inc" ; Also, actually this is function body.

;/*****************************************************************************
;*      FUNCTION :      StartUp()
;*      DESCRIPTION :   The initial starting point of the system
;*      INPUTS :        None - we are branched to from the reset vector
;*      OUTPUTS :       None, we branch to the main()
;*      CAUTIONS :      We are operating in CPU clock mode that specified by
;*                      switch S1-1, S1-2, and S1-3. CPG FRQCR is left keeping
;*                      reset value for the clock frexibility.
;*
;*    o Constructors are not initialized.  They aren't used by the bootloader.
;*
;*    o exit is not called.  There is no stdio library, etc., to close.
;*
;*    The bootloader is configured to run from RAM in memory section P1
;*    (cached) but the SH-4 boots in FLASH in section P2 (uncached).  Thus,
;*    the initial memory setup code below (up to the call to _main) must be
;*    position independent.
;*
;* Arguments:
;*
;*    None; we are branched to, not called.
;*
;* Return Value:
;*
;*    None; there is nothing to return to.
;*
;*****************************************************************************/

    LEAF_ENTRY _StartUp

    mov.l   #TM_SR, r0                  ; release mask etc
    ldc     r0, sr

    mov.l   #h'00000000, r0
    ldc     r0, vbr

    ; When the FRQCR is modified, it creates unstability in the PLL.  For this
    ; reason, when FRQCR is modified, the CPU shuts off.  The Watchdog timer
    ; is used to wake-up of the system, so it must be configured properly before
    ; setting FRQCR. At least 200us is needed for PLL stabilization.

    mov.l   #CPG_WTCSR, r1
    mov.w   #SET_CKS, r0
    mov.w   r0, @r1                     ; Set type of clock count to use in WTCSR
    mov.l   #CPG_WTCNT, r1
    mov.w   #COUNT_INIT, r0
    mov.w   r0, @r1                     ; Set initial value for counter in WTCNT

    ; Clock mode setting
;    mov.l   #CPG_FRQCR, r1
;    mov.l   #CPG_FRQCR_CLOCK, r0
;    mov.w   r0, @r1

    ; Bus timing configuration is moved to _ConfigureBusTimings.
    ; This detects operating clock frequency and configures hardware, then
    ; stores clock freqauency information to the driver global memory space.

    bsr     _ConfigureBusTimings
    nop

; The bootloader is linked to run from RAM but is initially installed in FLASH
; at the SH-4's boot address.  Now that memory has been configured, copy the
; entire bootloader image to RAM.
;
; N.B.  The bootloader's region size must agree with boot.bib's declaration of
; it.

    mov.l   #LOADER_BYTES/4,r0          ; Size of bootloader's region in dwords
    mov.l   #LOADER_ROM_ADDR, r1        ; Uncached alias of loader's FLASH addr
    mov.l   #LOADER_RAM_ADDR, r2        ; Uncached alias of loader's RAM address
CopyLoop:
    mov.l   @r1,r3                      ; Load next bootloader word
    add     #-1,r0                      ; 1 less word to copy
    mov.l   r3,@r2                      ; Store next bootloader word
    cmp/eq  #0,r0                       ; Done?
    add     #4,r1                       ; 4 more bytes loaded
    bf/s    CopyLoop                    ;   (more of Done?)
    add     #4,r2                       ; 4 more bytes stored

; Flush then enable the cache in copy-back mode.

    mov.l   #CCN_CCR, r1
    mov.l   #CCN_CCR_FLUSH, r0          ; Flush the cache
    mov.l   r0, @r1
    mov     #CCN_CCR_ENABLE, r0         ; Enable the cache
    mov.l   r0, @r1

    nop
    nop
    nop

    mov.l   #LOADER_STACK, r15          ; Set up a stack

; The bootloader is linked to run in section P1 (cached) but is started at
; reset in section P2 (uncached).  Now that memory has been configured and the
; cache turned on, the jsr to _main (an absolute address) also branches from
; section P2 to section P1, effectively enabling the cache at the same time.

    mov.l   #_main, r0                  ; Call main
    jsr     @r0                         ; Should never return
    nop

HaltLoop:
    bra     HaltLoop                    ; If return, spin forever
    nop

    ENTRY_END _StartUp

;++
;
; void Launch(
;    unsigned long pFunc
;    )
;
; Routine Description:
;
;    This function launches the program at pFunc.  The expectation is that
;    the launched program never returns.
;
; Arguments:
;
;    pFunc (r4) - Supplies the address of the program to launch.
;
; Return Value:
;
;    None; the launched program never returns.
;
;--

    LEAF_ENTRY _Launch
    jmp     @r4
    nop
    ENTRY_END _Launch

    LEAF_ENTRY _LaunchExisting
    jmp     @r4
    nop
    ENTRY_END _LaunchExisting
    
INDEX_REG_R0:   .equ 0
INDEX_REG_R1:   .equ 4
INDEX_REG_R2:   .equ 8
INDEX_REG_R3:   .equ 12
INDEX_REG_R4:   .equ 16
INDEX_REG_R5:   .equ 20
INDEX_REG_R6:   .equ 24
INDEX_REG_R7:   .equ 28
INDEX_REG_GBR:  .equ 32
INDEX_REG_MACH: .equ 36
INDEX_REG_MACL: .equ 40
INDEX_REG_PC:   .equ 44
INDEX_REG_PR:   .equ 48
INDEX_REG_SR:   .equ 52
INDEX_REG_SPR:  .equ 56
INDEX_REG_SSR:  .equ 60


; DEBUGTIME .equ 0                      ; Disable debug timing
DEBUGTIME   .equ 1                      ; Enable debug timing


    .aif DEBUGTIME
LoopCount .equ 50000000
    
    LEAF_ENTRY _Time1
    mov     #LoopCount,r0
T1Loop:
    dt      r0
    bf      T1Loop
    rts
     nop
    ENTRY_END _Time1
    
    LEAF_ENTRY _Time2
    mov     #LoopCount,r0
T2Loop:
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    dt      r0
    bf      T2Loop
    rts
     nop
    ENTRY_END _Time2
    
    LEAF_ENTRY _Time3
    mov     #LoopCount,r0
T3Loop:
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    dt      r0
    bf      T3Loop
    rts
     nop
    ENTRY_END _Time3
    .aendi

    .end