smc91c94.h

Wince4.2 BSP for SH4 engineering development board

//
//      Copyright (c) Renesas Technology Corp. 1999-2003 All Rights Reserved.
//
//      LAN91C111 network hardware driver
//
//----------------------------------------------------------------------------
//
//  FILE      : LAN91C94.H
//  CREATED   : 1999.04.26
//  MODIFIED  : 2003.08.06
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS HS7751RSTC01H (S1-E, ITS-DS5)
//  TARGET OS : Microsoft(R) Windows(R) CE .NET 4.2
//  FUNCTION  : Function prototypes and structures
//  HISTORY   : 
//              1999.04.26
//              - Released as SMSC LAN91C94 driver for PFM-DS6x.
//              (Detailed history for PFM-DS6x are omitted.)
//              2002.04.??
//              - Modified to LAN91C111 driver for HS7751RSTC01H.
//              2002.05.18
//              - Register access macros are modified from the bus width
//               change of 32bit to 16bit. 
//              2002.09.05
//              - Header style is changed and file informations are added.

#ifndef	_SMC91C94_H_
#define	_SMC91C94_H_

#define	BANK_SELECT		14

/* BANK 0  */

#define	TCR 		0    	/* transmit control register */
#define TCR_ENABLE	0x0001	/* if this is 1, we can transmit */ 
#define TCR_FDUPLX    	0x0800  /* receive packets sent out */
#define TCR_STP_SQET	0x1000	/* stop transmitting if Signal quality error */
#define	TCR_MON_CNS	0x0400	/* monitors the carrier status */
#define	TCR_PAD_ENABLE	0x0080	/* pads short packets to 64 bytes */
#define	TCR_LOOP	0x0002	/* Internal loopback mode */

#define	TCR_CLEAR	0	/* do NOTHING */
/* the normal settings for the TCR register : */ 
/* QUESTION: do I want to enable padding of short packets ? */
#define	TCR_NORMAL  	TCR_ENABLE 


#define EPH_STATUS	2
#define ES_LINK_OK	0x4000	/* is the link integrity ok ? */

#define	RCR		4
#define RCR_SOFTRESET	0x8000 	/* resets the chip */	
#define	RCR_STRIP_CRC	0x200	/* strips CRC */
#define RCR_ENABLE	0x100	/* IFF this is set, we can recieve packets */
#define RCR_ALMUL	0x4 	/* receive all multicast packets */
#define	RCR_PROMISC	0x2	/* enable promiscuous mode */

/* the normal settings for the RCR register : */
#define	RCR_NORMAL	(RCR_STRIP_CRC | RCR_ENABLE)
#define RCR_CLEAR	0x0		/* set it to a base state */

#define	COUNTER		6
#define	MIR		8
#define	MCR		10
/* 12 is reserved */

/* BANK 1 */
#define CONFIG			0
#define CFG_AUI_SELECT	 	0x0100
#define CFG_DISLINK	 	0x0040
#define	BASE			2
#define	ADDR0			4
#define	ADDR1			6
#define	ADDR2			8
#define	GENERAL			10
#define	CONTROL			12
#define	CTL_POWERDOWN		0x2000
#define	CTL_LE_ENABLE		0x80
#define	CTL_CR_ENABLE		0x40
#define	CTL_TE_ENABLE		0x0020
#define CTL_AUTO_RELEASE	0x0800
#define	CTL_EPROM_ACCESS	0x0003 /* high if Eprom is being read */

/* BANK 2 */
#define MMU_CMD		0
#define MC_BUSY		1	/* only readable bit in the register */
#define MC_NOP		0
#define	MC_ALLOC	0x20  	/* or with number of 256 byte packets */
#define	MC_RESET	0x40	
#define	MC_REMOVE	0x60  	/* remove the current rx packet */
#define MC_RELEASE  	0x80  	/* remove and release the current rx packet */
#define MC_FREEPKT  	0xA0  	/* Release packet in PNR register */
#define MC_ENQUEUE	0xC0 	/* Enqueue the packet for transmit */
 	
#define	PNR_ARR		2
#define FIFO_PORTS	4

#define FP_RXEMPTY  0x8000
#define FP_TXEMPTY  0x80

#define	POINTER		6
#define PTR_READ	0x2000
#define	PTR_RCV		0x8000
#define	PTR_AUTOINC 	0x4000
#define PTR_AUTO_INC	0x0040

#define	DATA_1		8
#define	DATA_2		10
#define	INT_REG		12

#define	RCV_INT		0x0001
#define	TX_INT		0x0002
#define	ALLOC_INT	0x0008
#define	TXEMPTY_INT	0x0004
#define	OVRN_INT	0x0010
#define	MD_INT		0x0080

#define INT_MASK	12
#define INT_ACK		13
#define IM_RCV_INT	0x0100
#define	IM_TX_INT	0x0200
#define	IM_TX_EMPTY_INT	0x0400	
#define	IM_ALLOC_INT	0x0800
#define	IM_RX_OVRN_INT	0x1000
#define	IM_EPH_INT	0x2000
#define	IM_ERCV_INT	0x4000 /* not on SMC9192 */		
#define IM_MD_INT	0x8000


/* BANK 3 */
#define	MULTICAST1	0
#define	MULTICAST2	2
#define	MULTICAST3	4
#define	MULTICAST4	6
#define	MGMT		8
#define	REVISION	10 /* ( hi: chip id   low: rev # ) */

#define	ERCV		12

#define CHIP_9190	3
#define CHIP_9194	4
#define CHIP_9195	5
#define CHIP_91100	7

static const char * chip_ids[ 15 ] =  { 
	NULL, NULL, NULL, 
	/* 3 */ "SMC91C90/91C92",
	/* 4 */ "SMC91C94",
	/* 5 */ "SMC91C95",
	NULL,
	/* 7 */ "SMC91C100", 
	NULL, NULL, NULL, NULL, 
	NULL, NULL, NULL};  

/* 
 . Transmit status bits 
*/
#define TS_SUCCESS 0x0001
#define TS_LOSTCAR 0x0400
#define TS_LATCOL  0x0200
#define TS_16COL   0x0010

/*
 . Receive status bits
*/
#define RS_ALGNERR	0x8000
#define RS_BADCRC	0x2000
#define RS_ODDFRAME	0x1000
#define RS_TOOLONG	0x0800
#define RS_TOOSHORT	0x0400
#define RS_MULTICAST	0x0001
#define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 

// These values are written to the bank select register to change banks.
#define BANK0 0x3300
#define BANK1 0x3301
#define BANK2 0x3302
#define BANK3 0x3303

// for HS7751RSTC01H
#define ReadWord(wOffset) (*((UINT16 volatile *)((EtherNetBase) + (wOffset))))
#define WriteWord( wOffset, Value ) (*((UINT16 volatile *)((EtherNetBase) + (wOffset))) = (Value))

#define SelectBank(Bank)	WriteWord(BANK_SELECT,Bank)

#endif	// _SMC91C94_H_