ddsfpga.map.qmsg

dds设计，生成多种波形，Verilog语言

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "romlookup romlookup:inst4 " "Info: Elaborating entity \"romlookup\" for hierarchy \"romlookup:inst4\"" {  } { { "DDSFPGA.bdf" "inst4" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 840 1472 1624 936 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram romlookup:inst4\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"romlookup:inst4\|altsyncram:altsyncram_component\"" {  } { { "romlookup.v" "altsyncram_component" { Text "E:/creat/altera/DDS/DDSFPGA/romlookup.v" 73 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_88s.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_88s.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_88s " "Info: Found entity 1: altsyncram_88s" {  } { { "db/altsyncram_88s.tdf" "" { Text "E:/creat/altera/DDS/DDSFPGA/db/altsyncram_88s.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_88s romlookup:inst4\|altsyncram:altsyncram_component\|altsyncram_88s:auto_generated " "Info: Elaborating entity \"altsyncram_88s\" for hierarchy \"romlookup:inst4\|altsyncram:altsyncram_component\|altsyncram_88s:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "control:inst1\|DLedout\[7\] High " "Info: Power-up level of register \"control:inst1\|DLedout\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 17 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "control:inst1\|DLedout\[7\] data_in VCC " "Warning: Reduced register \"control:inst1\|DLedout\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 17 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "squwave:inst5\|qsquare\[7\] squwave:inst5\|qsquare\[6\] " "Info: Duplicate register \"squwave:inst5\|qsquare\[7\]\" merged to single register \"squwave:inst5\|qsquare\[6\]\"" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "squwave:inst5\|qsquare\[5\] squwave:inst5\|qsquare\[6\] " "Info: Duplicate register \"squwave:inst5\|qsquare\[5\]\" merged to single register \"squwave:inst5\|qsquare\[6\]\"" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "squwave:inst5\|qsquare\[4\] squwave:inst5\|qsquare\[6\] " "Info: Duplicate register \"squwave:inst5\|qsquare\[4\]\" merged to single register \"squwave:inst5\|qsquare\[6\]\"" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "squwave:inst5\|qsquare\[3\] squwave:inst5\|qsquare\[6\] " "Info: Duplicate register \"squwave:inst5\|qsquare\[3\]\" merged to single register \"squwave:inst5\|qsquare\[6\]\"" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "squwave:inst5\|qsquare\[2\] squwave:inst5\|qsquare\[6\] " "Info: Duplicate register \"squwave:inst5\|qsquare\[2\]\" merged to single register \"squwave:inst5\|qsquare\[6\]\"" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "squwave:inst5\|qsquare\[1\] squwave:inst5\|qsquare\[6\] " "Info: Duplicate register \"squwave:inst5\|qsquare\[1\]\" merged to single register \"squwave:inst5\|qsquare\[6\]\"" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "squwave:inst5\|qsquare\[0\] squwave:inst5\|qsquare\[6\] " "Info: Duplicate register \"squwave:inst5\|qsquare\[0\]\" merged to single register \"squwave:inst5\|qsquare\[6\]\"" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|DDSFPGA\|control:inst1\|state_wave 3 0 " "Info: State machine \"\|DDSFPGA\|control:inst1\|state_wave\" contains 3 states and 0 state bits" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|DDSFPGA\|control:inst1\|state_adjust 3 0 " "Info: State machine \"\|DDSFPGA\|control:inst1\|state_adjust\" contains 3 states and 0 state bits" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DDSFPGA\|control:inst1\|state_wave " "Info: Selected Auto state machine encoding method for state machine \"\|DDSFPGA\|control:inst1\|state_wave\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DDSFPGA\|control:inst1\|state_wave " "Info: Encoding result for state machine \"\|DDSFPGA\|control:inst1\|state_wave\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "control:inst1\|state_wave.sin " "Info: Encoded state bit \"control:inst1\|state_wave.sin\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "control:inst1\|state_wave.triangle " "Info: Encoded state bit \"control:inst1\|state_wave.triangle\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "control:inst1\|state_wave.square " "Info: Encoded state bit \"control:inst1\|state_wave.square\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DDSFPGA\|control:inst1\|state_wave.square 000 " "Info: State \"\|DDSFPGA\|control:inst1\|state_wave.square\" uses code string \"000\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DDSFPGA\|control:inst1\|state_wave.triangle 011 " "Info: State \"\|DDSFPGA\|control:inst1\|state_wave.triangle\" uses code string \"011\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DDSFPGA\|control:inst1\|state_wave.sin 101 " "Info: State \"\|DDSFPGA\|control:inst1\|state_wave.sin\" uses code string \"101\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0}  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 25 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DDSFPGA\|control:inst1\|state_adjust " "Info: Selected Auto state machine encoding method for state machine \"\|DDSFPGA\|control:inst1\|state_adjust\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DDSFPGA\|control:inst1\|state_adjust " "Info: Encoding result for state machine \"\|DDSFPGA\|control:inst1\|state_adjust\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "control:inst1\|state_adjust.adj10k " "Info: Encoded state bit \"control:inst1\|state_adjust.adj10k\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "control:inst1\|state_adjust.adj100 " "Info: Encoded state bit \"control:inst1\|state_adjust.adj100\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "control:inst1\|state_adjust.adj1 " "Info: Encoded state bit \"control:inst1\|state_adjust.adj1\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DDSFPGA\|control:inst1\|state_adjust.adj10k 000 " "Info: State \"\|DDSFPGA\|control:inst1\|state_adjust.adj10k\" uses code string \"000\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DDSFPGA\|control:inst1\|state_adjust.adj100 110 " "Info: State \"\|DDSFPGA\|control:inst1\|state_adjust.adj100\" uses code string \"110\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DDSFPGA\|control:inst1\|state_adjust.adj1 101 " "Info: State \"\|DDSFPGA\|control:inst1\|state_adjust.adj1\" uses code string \"101\"" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0}  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 27 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DLedout\[7\] VCC " "Warning: Pin \"DLedout\[7\]\" stuck at VCC" {  } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "388 " "Info: Implemented 388 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "48 " "Info: Implemented 48 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "323 " "Info: Implemented 323 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 03 20:28:25 2006 " "Info: Processing ended: Wed May 03 20:28:25 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}