ddsfpga.map.qmsg

dds设计，生成多种波形，Verilog语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 03 20:28:19 2006 " "Info: Processing started: Wed May 03 20:28:19 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDSFPGA -c DDSFPGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDSFPGA -c DDSFPGA" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "romlookup.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file romlookup.v" { { "Info" "ISGN_ENTITY_NAME" "1 romlookup " "Info: Found entity 1: romlookup" {  } { { "romlookup.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/romlookup.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDSFPGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDSFPGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DDSFPGA " "Info: Found entity 1: DDSFPGA" {  } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key.v" { { "Info" "ISGN_ENTITY_NAME" "1 Key " "Info: Found entity 1: Key" {  } { { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control.v" { { "Info" "ISGN_ENTITY_NAME" "1 control " "Info: Found entity 1: control" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "squwave.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file squwave.v" { { "Info" "ISGN_ENTITY_NAME" "1 squwave " "Info: Found entity 1: squwave" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "triawave.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file triawave.v" { { "Info" "ISGN_ENTITY_NAME" "1 triawave " "Info: Found entity 1: triawave" {  } { { "triawave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/triawave.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "datachoose.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file datachoose.v" { { "Info" "ISGN_ENTITY_NAME" "1 datachoose " "Info: Found entity 1: datachoose" {  } { { "datachoose.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/datachoose.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_d2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock_d2.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_d2 " "Info: Found entity 1: clock_d2" {  } { { "clock_d2.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/clock_d2.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDSFPGA " "Info: Elaborating entity \"DDSFPGA\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datachoose datachoose:inst2 " "Info: Elaborating entity \"datachoose\" for hierarchy \"datachoose:inst2\"" {  } { { "DDSFPGA.bdf" "inst2" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 640 1752 1920 800 "inst2" "" } } } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "datachoose.v(13) " "Info: Verilog HDL Case Statement information at datachoose.v(13): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "datachoose.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/datachoose.v" 13 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_d2 clock_d2:inst " "Info: Elaborating entity \"clock_d2\" for hierarchy \"clock_d2:inst\"" {  } { { "DDSFPGA.bdf" "inst" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 600 832 928 696 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control control:inst1 " "Info: Elaborating entity \"control\" for hierarchy \"control:inst1\"" {  } { { "DDSFPGA.bdf" "inst1" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 688 1192 1384 816 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Key Key:inst3 " "Info: Elaborating entity \"Key\" for hierarchy \"Key:inst3\"" {  } { { "DDSFPGA.bdf" "inst3" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 704 960 1128 800 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "squwave squwave:inst5 " "Info: Elaborating entity \"squwave\" for hierarchy \"squwave:inst5\"" {  } { { "DDSFPGA.bdf" "inst5" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 600 1472 1656 696 "inst5" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triawave triawave:inst6 " "Info: Elaborating entity \"triawave\" for hierarchy \"triawave:inst6\"" {  } { { "DDSFPGA.bdf" "inst6" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 720 1472 1656 816 "inst6" "" } } } }  } 0}