ddsfpga.fit.summary

来自「dds设计，生成多种波形，Verilog语言」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Wed May 03 20:28:35 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : DDSFPGA
Top-level Entity Name : DDSFPGA
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 319 / 2,910 ( 10 % )
Total pins : 57 / 104 ( 54 % )
Total virtual pins : 0
Total memory bits : 8,192 / 59,904 ( 13 % )
Total PLLs : 0 / 1 ( 0 % )