ddsfpga.map.eqn

dds设计，生成多种波形，Verilog语言

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--D1_dataout[7] is datachoose:inst2|dataout[7]
--operation mode is normal

D1_dataout[7]_lut_out = C1_entri & (H1_qtriangle[7]) # !C1_entri & K1_q_a[7];
D1_dataout[7] = DFFEAS(D1_dataout[7]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--D1_dataout[6] is datachoose:inst2|dataout[6]
--operation mode is normal

D1_dataout[6]_lut_out = C1_entri & (H1_qtriangle[6]) # !C1_entri & K1_q_a[6];
D1_dataout[6] = DFFEAS(D1_dataout[6]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--D1_dataout[5] is datachoose:inst2|dataout[5]
--operation mode is normal

D1_dataout[5]_lut_out = C1_entri & (H1_qtriangle[5]) # !C1_entri & K1_q_a[5];
D1_dataout[5] = DFFEAS(D1_dataout[5]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--D1_dataout[4] is datachoose:inst2|dataout[4]
--operation mode is normal

D1_dataout[4]_lut_out = C1_entri & (H1_qtriangle[4]) # !C1_entri & K1_q_a[4];
D1_dataout[4] = DFFEAS(D1_dataout[4]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--D1_dataout[3] is datachoose:inst2|dataout[3]
--operation mode is normal

D1_dataout[3]_lut_out = C1_entri & (H1_qtriangle[3]) # !C1_entri & K1_q_a[3];
D1_dataout[3] = DFFEAS(D1_dataout[3]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--D1_dataout[2] is datachoose:inst2|dataout[2]
--operation mode is normal

D1_dataout[2]_lut_out = C1_entri & (H1_qtriangle[2]) # !C1_entri & K1_q_a[2];
D1_dataout[2] = DFFEAS(D1_dataout[2]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--D1_dataout[1] is datachoose:inst2|dataout[1]
--operation mode is normal

D1_dataout[1]_lut_out = C1_entri & (H1_qtriangle[1]) # !C1_entri & K1_q_a[1];
D1_dataout[1] = DFFEAS(D1_dataout[1]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--D1_dataout[0] is datachoose:inst2|dataout[0]
--operation mode is normal

D1_dataout[0]_lut_out = C1_entri & (H1_qtriangle[0]) # !C1_entri & K1_q_a[0];
D1_dataout[0] = DFFEAS(D1_dataout[0]_lut_out, B1_clk2, VCC, , , D1L1, , D1L6, C1_ensqu);


--C1_DLedout[6] is control:inst1|DLedout[6]
--operation mode is normal

C1_DLedout[6]_lut_out = C1L86 # C1_DLedout[6] & (!E1_nkeyout[7]);
C1_DLedout[6] = DFFEAS(C1_DLedout[6]_lut_out, B1_clk2, VCC, , , , , , );


--C1_DLedout[5] is control:inst1|DLedout[5]
--operation mode is normal

C1_DLedout[5]_lut_out = !E1_nkeyout[1] & !C1_state_adjust.adj10k;
C1_DLedout[5] = DFFEAS(C1_DLedout[5]_lut_out, B1_clk2, VCC, , A1L56, , , , );


--C1_DLedout[4] is control:inst1|DLedout[4]
--operation mode is normal

C1_DLedout[4]_lut_out = C1_state_adjust.adj100 & (!E1_nkeyout[1]);
C1_DLedout[4] = DFFEAS(C1_DLedout[4]_lut_out, B1_clk2, VCC, , A1L56, , , , );


--C1_DLedout[3] is control:inst1|DLedout[3]
--operation mode is normal

C1_DLedout[3]_lut_out = C1_state_adjust.adj1 & (!E1_nkeyout[1]);
C1_DLedout[3] = DFFEAS(C1_DLedout[3]_lut_out, B1_clk2, VCC, , A1L56, , , , );


--C1_DLedout[2] is control:inst1|DLedout[2]
--operation mode is normal

C1_DLedout[2]_lut_out = C1_state_wave.sin & (!E1_nkeyout[7]);
C1_DLedout[2] = DFFEAS(C1_DLedout[2]_lut_out, B1_clk2, VCC, , C1L16, , , , );


--C1_DLedout[1] is control:inst1|DLedout[1]
--operation mode is normal

C1_DLedout[1]_lut_out = C1L96;
C1_DLedout[1] = DFFEAS(C1_DLedout[1]_lut_out, B1_clk2, VCC, , C1L16, , , , );


--C1_DLedout[0] is control:inst1|DLedout[0]
--operation mode is normal

C1_DLedout[0]_lut_out = !C1L07;
C1_DLedout[0] = DFFEAS(C1_DLedout[0]_lut_out, B1_clk2, VCC, , C1L16, , , , );


--E1_nkeyout[7] is Key:inst3|nkeyout[7]
--operation mode is normal

E1_nkeyout[7]_lut_out = KeyIn[7] & E1L91 & E1L8;
E1_nkeyout[7] = DFFEAS(E1_nkeyout[7]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--E1_nkeyout[6] is Key:inst3|nkeyout[6]
--operation mode is normal

E1_nkeyout[6]_lut_out = KeyIn[6] & E1L91 & E1L8;
E1_nkeyout[6] = DFFEAS(E1_nkeyout[6]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--E1_nkeyout[5] is Key:inst3|nkeyout[5]
--operation mode is normal

E1_nkeyout[5]_lut_out = KeyIn[5] & E1L91 & E1L8;
E1_nkeyout[5] = DFFEAS(E1_nkeyout[5]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--E1_nkeyout[4] is Key:inst3|nkeyout[4]
--operation mode is normal

E1_nkeyout[4]_lut_out = KeyIn[4] & E1L91 & E1L8;
E1_nkeyout[4] = DFFEAS(E1_nkeyout[4]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--E1_nkeyout[3] is Key:inst3|nkeyout[3]
--operation mode is normal

E1_nkeyout[3]_lut_out = KeyIn[3] & E1L91 & E1L8;
E1_nkeyout[3] = DFFEAS(E1_nkeyout[3]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--E1_nkeyout[2] is Key:inst3|nkeyout[2]
--operation mode is normal

E1_nkeyout[2]_lut_out = KeyIn[2] & E1L91 & E1L8;
E1_nkeyout[2] = DFFEAS(E1_nkeyout[2]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--E1_nkeyout[1] is Key:inst3|nkeyout[1]
--operation mode is normal

E1_nkeyout[1]_lut_out = KeyIn[1] & E1L91 & E1L8;
E1_nkeyout[1] = DFFEAS(E1_nkeyout[1]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--E1_nkeyout[0] is Key:inst3|nkeyout[0]
--operation mode is normal

E1_nkeyout[0]_lut_out = KeyIn[0] & E1L91 & E1L8;
E1_nkeyout[0] = DFFEAS(E1_nkeyout[0]_lut_out, B1_clk2, VCC, , E1L81, , , , );


--K1_q_a[7] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[7]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[7]_PORT_A_address_reg = DFFE(K1_q_a[7]_PORT_A_address, K1_q_a[7]_clock_0, , , K1_q_a[7]_clock_enable_0);
K1_q_a[7]_clock_0 = B1_clk2;
K1_q_a[7]_clock_enable_0 = C1_ensin;
K1_q_a[7]_PORT_A_data_out = MEMORY(, , K1_q_a[7]_PORT_A_address_reg, , , , , , K1_q_a[7]_clock_0, , K1_q_a[7]_clock_enable_0, , , );
K1_q_a[7]_PORT_A_data_out_reg = DFFE(K1_q_a[7]_PORT_A_data_out, K1_q_a[7]_clock_0, , , K1_q_a[7]_clock_enable_0);
K1_q_a[7] = K1_q_a[7]_PORT_A_data_out_reg[0];


--K1_q_a[6] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[6]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[6]_PORT_A_address_reg = DFFE(K1_q_a[6]_PORT_A_address, K1_q_a[6]_clock_0, , , K1_q_a[6]_clock_enable_0);
K1_q_a[6]_clock_0 = B1_clk2;
K1_q_a[6]_clock_enable_0 = C1_ensin;
K1_q_a[6]_PORT_A_data_out = MEMORY(, , K1_q_a[6]_PORT_A_address_reg, , , , , , K1_q_a[6]_clock_0, , K1_q_a[6]_clock_enable_0, , , );
K1_q_a[6]_PORT_A_data_out_reg = DFFE(K1_q_a[6]_PORT_A_data_out, K1_q_a[6]_clock_0, , , K1_q_a[6]_clock_enable_0);
K1_q_a[6] = K1_q_a[6]_PORT_A_data_out_reg[0];


--K1_q_a[5] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[5]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[5]_PORT_A_address_reg = DFFE(K1_q_a[5]_PORT_A_address, K1_q_a[5]_clock_0, , , K1_q_a[5]_clock_enable_0);
K1_q_a[5]_clock_0 = B1_clk2;
K1_q_a[5]_clock_enable_0 = C1_ensin;
K1_q_a[5]_PORT_A_data_out = MEMORY(, , K1_q_a[5]_PORT_A_address_reg, , , , , , K1_q_a[5]_clock_0, , K1_q_a[5]_clock_enable_0, , , );
K1_q_a[5]_PORT_A_data_out_reg = DFFE(K1_q_a[5]_PORT_A_data_out, K1_q_a[5]_clock_0, , , K1_q_a[5]_clock_enable_0);
K1_q_a[5] = K1_q_a[5]_PORT_A_data_out_reg[0];


--K1_q_a[4] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[4]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[4]_PORT_A_address_reg = DFFE(K1_q_a[4]_PORT_A_address, K1_q_a[4]_clock_0, , , K1_q_a[4]_clock_enable_0);
K1_q_a[4]_clock_0 = B1_clk2;
K1_q_a[4]_clock_enable_0 = C1_ensin;
K1_q_a[4]_PORT_A_data_out = MEMORY(, , K1_q_a[4]_PORT_A_address_reg, , , , , , K1_q_a[4]_clock_0, , K1_q_a[4]_clock_enable_0, , , );
K1_q_a[4]_PORT_A_data_out_reg = DFFE(K1_q_a[4]_PORT_A_data_out, K1_q_a[4]_clock_0, , , K1_q_a[4]_clock_enable_0);
K1_q_a[4] = K1_q_a[4]_PORT_A_data_out_reg[0];


--K1_q_a[3] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[3]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[3]_PORT_A_address_reg = DFFE(K1_q_a[3]_PORT_A_address, K1_q_a[3]_clock_0, , , K1_q_a[3]_clock_enable_0);
K1_q_a[3]_clock_0 = B1_clk2;
K1_q_a[3]_clock_enable_0 = C1_ensin;
K1_q_a[3]_PORT_A_data_out = MEMORY(, , K1_q_a[3]_PORT_A_address_reg, , , , , , K1_q_a[3]_clock_0, , K1_q_a[3]_clock_enable_0, , , );
K1_q_a[3]_PORT_A_data_out_reg = DFFE(K1_q_a[3]_PORT_A_data_out, K1_q_a[3]_clock_0, , , K1_q_a[3]_clock_enable_0);
K1_q_a[3] = K1_q_a[3]_PORT_A_data_out_reg[0];


--K1_q_a[2] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[2]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[2]_PORT_A_address_reg = DFFE(K1_q_a[2]_PORT_A_address, K1_q_a[2]_clock_0, , , K1_q_a[2]_clock_enable_0);
K1_q_a[2]_clock_0 = B1_clk2;
K1_q_a[2]_clock_enable_0 = C1_ensin;
K1_q_a[2]_PORT_A_data_out = MEMORY(, , K1_q_a[2]_PORT_A_address_reg, , , , , , K1_q_a[2]_clock_0, , K1_q_a[2]_clock_enable_0, , , );
K1_q_a[2]_PORT_A_data_out_reg = DFFE(K1_q_a[2]_PORT_A_data_out, K1_q_a[2]_clock_0, , , K1_q_a[2]_clock_enable_0);
K1_q_a[2] = K1_q_a[2]_PORT_A_data_out_reg[0];


--K1_q_a[1] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[1]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[1]_PORT_A_address_reg = DFFE(K1_q_a[1]_PORT_A_address, K1_q_a[1]_clock_0, , , K1_q_a[1]_clock_enable_0);
K1_q_a[1]_clock_0 = B1_clk2;
K1_q_a[1]_clock_enable_0 = C1_ensin;
K1_q_a[1]_PORT_A_data_out = MEMORY(, , K1_q_a[1]_PORT_A_address_reg, , , , , , K1_q_a[1]_clock_0, , K1_q_a[1]_clock_enable_0, , , );
K1_q_a[1]_PORT_A_data_out_reg = DFFE(K1_q_a[1]_PORT_A_data_out, K1_q_a[1]_clock_0, , , K1_q_a[1]_clock_enable_0);
K1_q_a[1] = K1_q_a[1]_PORT_A_data_out_reg[0];


--K1_q_a[0] is romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
K1_q_a[0]_PORT_A_address = BUS(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7], C1_address[8], C1_address[9]);
K1_q_a[0]_PORT_A_address_reg = DFFE(K1_q_a[0]_PORT_A_address, K1_q_a[0]_clock_0, , , K1_q_a[0]_clock_enable_0);
K1_q_a[0]_clock_0 = B1_clk2;
K1_q_a[0]_clock_enable_0 = C1_ensin;
K1_q_a[0]_PORT_A_data_out = MEMORY(, , K1_q_a[0]_PORT_A_address_reg, , , , , , K1_q_a[0]_clock_0, , K1_q_a[0]_clock_enable_0, , , );
K1_q_a[0]_PORT_A_data_out_reg = DFFE(K1_q_a[0]_PORT_A_data_out, K1_q_a[0]_clock_0, , , K1_q_a[0]_clock_enable_0);
K1_q_a[0] = K1_q_a[0]_PORT_A_data_out_reg[0];


--G1_qsquare[6] is squwave:inst5|qsquare[6]
--operation mode is normal

G1_qsquare[6]_lut_out = !C1_address[9] & (C1_ensqu);
G1_qsquare[6] = DFFEAS(G1_qsquare[6]_lut_out, B1_clk2, VCC, , , , , , );


--H1_qtriangle[7] is triawave:inst6|qtriangle[7]
--operation mode is normal

H1_qtriangle[7]_lut_out = C1_address[8] $ C1_address[9];
H1_qtriangle[7] = DFFEAS(H1_qtriangle[7]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--H1_qtriangle[6] is triawave:inst6|qtriangle[6]
--operation mode is normal

H1_qtriangle[6]_lut_out = C1_address[7] $ C1_address[9];
H1_qtriangle[6] = DFFEAS(H1_qtriangle[6]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--H1_qtriangle[5] is triawave:inst6|qtriangle[5]
--operation mode is normal

H1_qtriangle[5]_lut_out = C1_address[6] $ C1_address[9];
H1_qtriangle[5] = DFFEAS(H1_qtriangle[5]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--H1_qtriangle[4] is triawave:inst6|qtriangle[4]
--operation mode is normal

H1_qtriangle[4]_lut_out = C1_address[5] $ C1_address[9];
H1_qtriangle[4] = DFFEAS(H1_qtriangle[4]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--H1_qtriangle[3] is triawave:inst6|qtriangle[3]
--operation mode is normal

H1_qtriangle[3]_lut_out = C1_address[4] $ C1_address[9];
H1_qtriangle[3] = DFFEAS(H1_qtriangle[3]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--H1_qtriangle[2] is triawave:inst6|qtriangle[2]
--operation mode is normal

H1_qtriangle[2]_lut_out = C1_address[3] $ C1_address[9];
H1_qtriangle[2] = DFFEAS(H1_qtriangle[2]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--H1_qtriangle[1] is triawave:inst6|qtriangle[1]
--operation mode is normal

H1_qtriangle[1]_lut_out = C1_address[2] $ C1_address[9];
H1_qtriangle[1] = DFFEAS(H1_qtriangle[1]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--H1_qtriangle[0] is triawave:inst6|qtriangle[0]
--operation mode is normal

H1_qtriangle[0]_lut_out = C1_address[1] $ C1_address[9];
H1_qtriangle[0] = DFFEAS(H1_qtriangle[0]_lut_out, B1_clk2, VCC, , , , , !C1_entri, );


--B1_clk2 is clock_d2:inst|clk2
--operation mode is normal

B1_clk2_lut_out = !B1_clk2;
B1_clk2 = DFFEAS(B1_clk2_lut_out, clk, VCC, , , , , , );


--C1_entri is control:inst1|entri
--operation mode is normal

C1_entri_lut_out = C1_state_wave.triangle;
C1_entri = DFFEAS(C1_entri_lut_out, B1_clk2, VCC, , !C1L273, , , , );


--C1_ensin is control:inst1|ensin
--operation mode is normal

C1_ensin_lut_out = C1_state_wave.sin;
C1_ensin = DFFEAS(C1_ensin_lut_out, B1_clk2, VCC, , !C1L273, , , , );


--D1L1 is datachoose:inst2|Select~465
--operation mode is normal

D1L1 = G1_qsquare[6] & (!C1_entri & !C1_ensin);


--C1_ensqu is control:inst1|ensqu
--operation mode is normal

C1_ensqu_lut_out = !C1_state_wave.square;
C1_ensqu = DFFEAS(C1_ensqu_lut_out, B1_clk2, VCC, , !C1L273, , , , );


--D1L6 is datachoose:inst2|dataout[2]~33
--operation mode is normal

D1L6 = !C1_ensqu & (C1_entri $ !C1_ensin);


--C1L86 is control:inst1|DLedout~121
--operation mode is normal

C1L86 = !E1_nkeyout[1] & (E1_nkeyout[3] # E1_nkeyout[2]);


--C1_state_adjust.adj10k is control:inst1|state_adjust.adj10k
--operation mode is normal

C1_state_adjust.adj10k_lut_out = !C1_state_adjust.adj100;
C1_state_adjust.adj10k = DFFEAS(C1_state_adjust.adj10k_lut_out, B1_clk2, VCC, , E1_nkeyout[1], , , , );


--A1L56 is rtl~4
--operation mode is normal

A1L56 = E1_nkeyout[7] # !E1_nkeyout[1];


--C1_state_adjust.adj100 is control:inst1|state_adjust.adj100
--operation mode is normal

C1_state_adjust.adj100_lut_out = C1_state_adjust.adj1;
C1_state_adjust.adj100 = DFFEAS(C1_state_adjust.adj100_lut_out, B1_clk2, VCC, , E1_nkeyout[1], , , , );


--C1_state_adjust.adj1 is control:inst1|state_adjust.adj1
--operation mode is normal

C1_state_adjust.adj1_lut_out = !C1_state_adjust.adj10k;
C1_state_adjust.adj1 = DFFEAS(C1_state_adjust.adj1_lut_out, B1_clk2, VCC, , E1_nkeyout[1], , , , );


--C1_state_wave.sin is control:inst1|state_wave.sin
--operation mode is normal

C1_state_wave.sin_lut_out = C1L96;
C1_state_wave.sin = DFFEAS(C1_state_wave.sin_lut_out, B1_clk2, VCC, , C1L273, , , , );


--C1L16 is control:inst1|DLedout[0]~124
--operation mode is normal

C1L16 = E1_nkeyout[7] # !E1_nkeyout[0];


--C1_state_wave.triangle is control:inst1|state_wave.triangle
--operation mode is normal