top.vhdl

FPGA向CY7C68013接收发送数据的代码,可以用LED显示

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
  port( clk  : in std_logic;
        slrd: buffer std_logic;	 -- read strobe
	   sloe: out std_logic;	      -- output enable
	   fifoaddr: out std_logic_vector(1 downto 0);
	   fifodata: in std_logic_vector(7 downto 0);   -- out data
        empty_flag : in std_logic;	  -- FLAGC
	   led: out std_logic_vector(7 downto 0)  -- no ";"
	   ) ;       
end top;


architecture Behavioral of top is
--type myarray is array	(511 downto 0) of std_logic_vector(7 downto 0);
--signal  data   : myarray ;
signal count : std_logic_vector(6 downto 0);
signal  inclk: std_logic;
signal flag:  std_logic;
signal insloe,inslrd: std_logic;
signal i: 	integer := 0;
signal firstdata: std_logic_vector(7 downto 0);
 
begin
process(clk)
  begin
    if clk'event and clk='1' then
	  count<=count+'1'; 
	 end if;
  end process;

fifoaddr<="00";  -- 地址应该为EP2
slrd<=inclk and inslrd;
sloe<=inclk and insloe;
inclk<=count(6);	
flag<=empty_flag; --and start;
led<=firstdata;

	process(inclk)
	begin
	if(inclk'event and inclk='0') then

	    			if flag='1' then	   -- check empty flag
					insloe<='1';      -- not empty 
					inslrd<='1';      -- assert then deassert SLWR
					case i is 
						when 0		=> firstdata <= fifodata;
									   i <= i+1;
						when 511		=> i <= 0;
						when others 	=> i <= i+1;
					end case;	

	     		else 
		  			inslrd<='0';
					insloe<='0';
	     		end if;


	    	end if;

	end process;

end 	 Behavioral;