top.par

FPGA向CY7C68013接收发送数据的代码,可以用LED显示

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

CAOLIU::  Mon Nov 13 11:11:02 2006


E:/install/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd
top.ncd top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
E:/install/Xilinx.
Device speed data version:  ADVANCED 1.29 2003-12-13.


Resolved that IOB <led<0>> must be placed at site P111.
Resolved that IOB <led<1>> must be placed at site P113.
Resolved that IOB <led<2>> must be placed at site P114.
Resolved that IOB <clk> must be placed at site P80.
Resolved that IOB <led<3>> must be placed at site P115.
Resolved that IOB <led<4>> must be placed at site P116.
Resolved that IOB <led<5>> must be placed at site P117.
Resolved that IOB <led<6>> must be placed at site P119.
Resolved that IOB <led<7>> must be placed at site P120.
Resolved that IOB <empty_flag> must be placed at site P185.
Resolved that IOB <fifoaddr<0>> must be placed at site P181.
Resolved that IOB <sloe> must be placed at site P182.
Resolved that IOB <fifoaddr<1>> must be placed at site P180.
Resolved that IOB <slrd> must be placed at site P165.
Resolved that IOB <fifodata<0>> must be placed at site P168.
Resolved that IOB <fifodata<1>> must be placed at site P169.
Resolved that IOB <fifodata<2>> must be placed at site P171.
Resolved that IOB <fifodata<3>> must be placed at site P172.
Resolved that IOB <fifodata<4>> must be placed at site P196.
Resolved that IOB <fifodata<5>> must be placed at site P194.
Resolved that IOB <fifodata<6>> must be placed at site P191.
Resolved that IOB <fifodata<7>> must be placed at site P190.


Device utilization summary:

   Number of External IOBs            22 out of 141    15%
      Number of LOCed External IOBs   22 out of 22    100%

   Number of Slices                   34 out of 3584    1%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989742) REAL time: 0 secs 

.
Phase 3.8
.
Phase 3.8 (Checksum:993d23) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 213 unrouted;       REAL time: 2 secs 

Phase 2: 176 unrouted;       REAL time: 2 secs 

Phase 3: 24 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX1| No   |    4 |  0.000     |  0.614      |
+-------------------------+----------+------+------+------------+-------------+
|          count<6>       |   Local  |      |   29 |  0.318     |  2.827      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 194


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.293
   The MAXIMUM PIN DELAY IS:                               3.536
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.237

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         143           7          47          16           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  68 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.